Class 365/203 - Precharge

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter wherein circuit lines or elements are charged
No. of patents: 3007
Last issue date: 05/15/2012

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Number	Title	Issue Date
7352649	High speed array pipeline architecture A memory device including a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output l...	04/01/2008
7352626	Voltage regulator with less overshoot and faster settling time A voltage regulator may include an operational-amplifier section, a capacitor connected to an output of the operational-amplifier section, and a switch configured to connect the capacitor to a voltage supply. The switch is configured to charge the capacitor before a...	04/01/2008
7349274	Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit l...	03/25/2008
7349275	Semiconductor memory A system in which an overdrive period in a DRAM may be provided without providing for accurate delay time. There are provided MOS transistor TP1, capacitor C1, MOS transistor TP2, and control circuit. MOS transistor TP1 is turned on when ...	03/25/2008
7349288	Ultra high-speed Nor-type LSDL/Domino combined address decoder An ultra high speed address decoder uses a combination of Domino logic circuits and LSDL logic circuits. N address bits are converted into N logic true address bits and N complementary address bits. A partial address decoder generates two bit groups using selected o...	03/25/2008
7350018	Method and system for using dynamic random access memory as cache memory A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the ...	03/25/2008
7349267	Semiconductor memory device In a memory cell array, source lines are provided so that each of the source lines is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a gro...	03/25/2008
7349266	Memory device with a data hold latch A memory device includes a plurality of pairs of complimentary bit lines and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of memory cells. Each latch circuit has an input coupled to a data line ...	03/25/2008
7349270	Semiconductor memory with wordline timing A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low...	03/25/2008
7345916	Method and apparatus for high voltage operation for a high performance semiconductor memory device A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuo...	03/18/2008
7345936	Data storage circuit A data storage circuit having a plurality of memory cells (S1), a plurality of bit lines (BL, /BL) and a precharge circuit further comprises a discharge circuit. In an operating mode of the data storage circuit, the bit lines (BL, /BL) are precharged by the p...	03/18/2008
7345937	Open digit line array architecture for a memory array A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and...	03/18/2008
7342839	Memory cell access circuit A circuit for accessing a memory cell includes a local bitline and a local sense amplifier having a plurality of transistors. The local bitline may be connect the memory cell and the sense amplifier. A first global bitline may be connected to a first one of the plur...	03/11/2008
7342832	Bit line pre-settlement circuit and method for flash memory sensing scheme A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to-voltage converters, each of which generates an output voltage based upon the input current f...	03/11/2008
7342814	Content addressable memory with reduced search current and power The power required to search a content addressable memory (CAM) is substantially reduced by forming the CAM to have a number of CAM banks with a corresponding number of power switches that control power to the CAM banks, and then controlling the power to search the ...	03/11/2008
7342408	Semiconductor test device using leakage current and compensation system of leakage current The present invention relates to a semiconductor test device which may use a leakage current and/or a compensation system of leakage current. The semiconductor test device, according to exemplary embodiments of the present invention, may include MOS transistors whic...	03/11/2008
7342846	Address decoding systems and methods Systems and methods provide improved address decoding techniques for memory. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an address register that receives a reset signal, a clock signal, and an address signa...	03/11/2008
7340653	Method for testing a memory device Disclosed is a method for testing a memory device with a long-term clock signal by automatically performing precharge only after activation. In this method, a signal for precharging the banks of the memory device is automatically generated only at the falling edge o...	03/04/2008
7339845	Memory device A memory device an array of memory cells, the array including word lines and bit lines. The memory device also includes managing logic for managing array reading operations that are carried out by executing a step of precharging the bit lines and a step of turning o...	03/04/2008
7339815	Method of operating a programmable resistance memory array A method of operating a programmable resistance memory array. The method comprises writing to all of the programmable resistance elements within the same row of the memory array at substantially the same time. The programmable resistance elements preferably include ...	03/04/2008
7339846	Method and apparatus for reading data from nonvolatile memory Roughly described, a memory includes first and second target memory cells in a plurality of electrically adjacent memory cells all sharing a word line. The two target memory cells are separated from each other by at least one additional memory cell, and first curren...	03/04/2008
7339847	BLEQ driving circuit in semiconductor memory device A bit line equalization signal (BLEQ) driving circuit for generating an equalization signal used to perform a precharge operation in a semiconductor memory device includes a second boosted voltage generator for producing a second boosted voltage by pumping a supply ...	03/04/2008
7339839	Triggering of IO equilibrating ending signal with firing of column access signal A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of th...	03/04/2008
RE40132	Large scale integrated circuit with sense amplifier circuits for low voltage operation Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply vo...	03/04/2008
7339838	Method and apparatus for supplementary command bus An electronic system according to various aspects of the present invention includes a memory having a location-specific command interface and a general command interface. The memory communicates with other components in the system via a main command bus configured t...	03/04/2008
7339833	Non-volatile semiconductor memory device Using charges accumulated in a capacitance element connected to a drain side node of a memory cell, data is written in accordance with source side injection method. The capacitance value of the capacitance element is changed in accordance with the value of write dat...	03/04/2008
7337241	Fast-path apparatus for receiving data corresponding to a TCP connection A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packe...	02/26/2008
7336517	Physical priority encoder A priority encoder can be used for a Content-Addressable Memory (CAM) device that typically has an array of CAM cells arranged in columns and rows with each row having a match signal indicative that compare data has matched data within the respective row. A priority...	02/26/2008
7336546	Global bit select circuit with dual read and write bit line pairs A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit. ...	02/26/2008
7336106	Phase detector and method having hysteresis characteristics A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a seco...	02/26/2008
7336551	Semiconductor memory devices and systems, and methods of using having reduced timers and registers A device including a command decoder to receive a compound command, a timer to begin operating if the compound command includes an activate command and a precharge command, the timer to begin operating at substantially the same time as the activate command is issued...	02/26/2008
7336552	Sense amplifier connecting/disconnecting circuit arrangement and method for operating such a circuit arrangement An apparatus and method for operating a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including a switching device for connecting/disconnecting a sense amplifier to/from a bit line of a first cell fiel...	02/26/2008
7336518	Layout for equalizer and data line sense amplifier employed in a high speed memory device A memory device includes a memory cell array block including memory cells, a word line driver block adjacent the memory cell array block disposed in a direction in which word lines of the memory cells are arranged, a sense amplifier block adjacent the memory cell ar...	02/26/2008
7332769	Non-volatile memory arrangement having nanocrystals The amount of current flowing in the bitline during reading of a memory cell which is in the conductive state, hereinafter called the memory cell current, can be amplified manifold by changing the above mentioned select transistors to a novel device which is describ...	02/19/2008
7333387	Device and method for selecting 1-row and 2-row activation I claim a device and method for selecting 1-row and 2-row activation. A device includes a memory block array including a plurality of memory blocks arranged in a row-column format, a plurality of local inter-connectors to selectively couple upper local lines to lowe...	02/19/2008
7333358	Memory element A memory element having a first and second logic components, each having a first input, a second input, and an output. The first input of each of the logic components is connected to the output of the other logic component. The second inputs of each of the logic com...	02/19/2008
7332937	Dynamic logic with adaptive keeper Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit. Included is a leakage indicator circuit to model leakage in at least a por...	02/19/2008
7333378	Memory device that recycles a signal charge A semiconductor memory device having a shared sense amplifier architecture includes a bitline equalizing voltage generator, which recycles a boost voltage to generate bitline equalizing voltage. The bitline equalizing voltage is used to generate signals for activati...	02/19/2008
7333098	Active matrix display apparatus and method for improved uniformity An active matrix display apparatus is disclosed which can achieve significant improvement in uniformity. The display apparatus uses a horizontal driving circuit to which a precharge function is provided additionally. The horizontal driving circuit applies double sam...	02/19/2008
7330375	Sense amplifier circuit for parallel sensing of four current levels A single-ended sense amplifier having a precharge circuit for maintaining a stable voltage on a bitline, and a sensing circuit coupled to the bitline for sensing an amount of current flowing into the bitline. To sense multiple current levels and multiple stored bits...	02/12/2008

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Class 365/203 - Precharge