Bizarre Patents
A forehead support apparatus for resting a standing users forehead against a wall above a bathroom commode or urinal or beneath a showerhead.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7257041 | Memory circuit and related method for integrating pre-decoding and selective pre-charging In a memory circuit, memory cells are arranged in a matrix by “row line-and column line” (may also denoted as “word line and bit line”). The invention provides a memory circuit and related method capable for independently pre-charging the column lines or bit... | 08/14/2007 |
| 7257047 | Page buffer circuit of flash memory device with improved read operation function and method of controlling read operation thereof A page buffer circuit of a flash memory device includes page buffers which are connected to the plurality of bit line pairs, respectively, and execute a read operation or a program operation on memory cells in response to bit line control signals, bit line select si... | 08/14/2007 |
| 7254690 | Pipelined semiconductor memories and systems The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or... | 08/07/2007 |
| 7254072 | Semiconductor memory device having hierarchically structured data lines and precharging means A semiconductor memory device is provided comprising precharge circuits corresponding to global data line pairs, but not a precharge circuit corresponding to a local data line pair. In a command waiting state, data line selection switches are controlled to be in a c... | 08/07/2007 |
| 7254073 | Memory device having an array of resistive memory cells A memory device including an array of resistive memory cells, which are arranged in columns and rows, and wherein each resistive memory cell each is connected to a word line, to a bit line, and to a reference electrode. The word lines are assigned to the rows and th... | 08/07/2007 |
| 7254067 | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low wr... | 08/07/2007 |
| 7254069 | Semiconductor memory device storing redundant replacement information with small occupation area Column redundancy data storage circuit blocks storing column redundancy data for repairing defective columns are arranged in correspondence to respective memory cell array blocks. The storage data of the column redundancy data storage circuits is transferred to redu... | 08/07/2007 |
| 7254088 | Semiconductor memory In a multiport memory, in the event of simultaneous read/write operation for the same row address, a read word line pulse signal, output from a read control circuit for memory access based on an externally supplied read enable signal and read clock signal, is input ... | 08/07/2007 |
| 7251148 | Matchline sense circuit and method A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. ... | 07/31/2007 |
| 7251177 | Skewed sense AMP for variable resistance memory sensing A variable resistance memory sense amplifier has a built-in offset to assist in switching the sense amplifier when a resistive memory cell is in a low resistance state. The built-in offset can be achieved by varying size, threshold voltage, associated capacity or as... | 07/31/2007 |
| 7251183 | Static random access memory having a memory cell operating voltage larger than an operating voltage of a peripheral circuit A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage n... | 07/31/2007 |
| 7251184 | Semiconductor memory device A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarray 12 includes a first MOS transistor PD1 for charging a main bit line MBL1 and a ... | 07/31/2007 |
| 7251157 | Semiconductor device Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory... | 07/31/2007 |
| 7251194 | Memory system and method for strobing data, command and address signals A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory de... | 07/31/2007 |
| 7251174 | Semiconductor memory device for low power system A semiconductor memory device for outputting or storing a data in response to inputted address and command includes a first cell array for outputting the data to one of a bit line and a bit line bar; a first reference cell block for outputting a reference signal to ... | 07/31/2007 |
| 7251169 | Voltage supply circuit and semiconductor memory Each of first and second differential amplifiers has a function of increasing a bias current in response to the activation of a drivability control signal. A first driving circuit connects an output node to a high power supply line in response to the activation of a... | 07/31/2007 |
| 7251147 | Content comparator memory (CCM) device and method of operation A content comparator memory (CCM) device can include a row (100) of CCM cells (102-1 to 102-I). Each CCM cell (102-1 to 102-I) can have a controllable signal path (104-1 to 104-I) arranged in seri... | 07/31/2007 |
| 7248535 | Semiconductor memory devices having negatively biased sub word line scheme and methods of driving the same Semiconductor memory devices having a negatively biased sub-word line scheme and methods of driving the same are disclosed. In a semiconductor memory device, NMOS transistors for pulling down a word line enable signal and a word line driving signal to a negative vol... | 07/24/2007 |
| 7248512 | Semiconductor memory device having controller with improved current consumption A semiconductor memory device wherein, in order to control the current consumed in a column address counter and latch block in a read operation, delay units disposed in the column address counter and latch block perform a shifting operation according to a signal CAS... | 07/24/2007 |
| 7248534 | Semiconductor memory device A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-... | 07/24/2007 |
| 7248500 | Nonvolatile semiconductor memory device having reduced dependency of a source resistance on a position in an array A dummy cell having a low threshold voltage is disposed in a memory cell array in alignment with a memory cell. A dummy cell with a low threshold voltage adjacent to a selected memory cell column is selected, and a source-side local bit line of the selected memory c... | 07/24/2007 |
| 7248517 | Semiconductor memory device having local data line pair with delayed precharge voltage application point Disclosed herein is a semiconductor memory device having a pair of local data lines with a delayed precharge voltage application point. The semiconductor memory device of the present invention includes a delay block for delaying the activation time of a block write ... | 07/24/2007 |
| 7248507 | CMIS semiconductor nonvolatile storage circuit A nonvolatile semiconductor memory circuit includes a selection line, a first bit line, a second bit line, a first MIS transistor having a first gate coupled to the selection line, a first drain coupled to the first bit line via a first node, and a first source coup... | 07/24/2007 |
| 7248494 | Semiconductor memory device capable of compensating for leakage current A semiconductor memory device compensates leakage current. A plurality of memory cells is disposed at intersections of word lines and bit lines. A plurality of dummy cells is connected to at least one dummy bit line. A leakage compensation circuit is connected to th... | 07/24/2007 |
| 7248520 | Semiconductor memory and data read method of the same A semiconductor memory having memory cells each storing first data and second data in a memory cell array arranged in a column direction; a plurality of word lines connected to the memory cells in a row direction; and first and second bit lines, to which the first a... | 07/24/2007 |
| 7248518 | Self-timed memory device providing adequate charging time for selected heaviest loading row The invention includes an apparatus and method of selecting memory cells within a memory array. The method includes receiving a memory cell address. A column address and a row address are generated from the memory cell address. Row select lines or column select line... | 07/24/2007 |
| 7248519 | Semiconductor device that initializes memory cells of an activated wordline group A semiconductor device that initializes memory cells of an activated wordline group is provided. The device includes: a control signal generation circuit, which generates first and second control signals based on an activated setting signal and an initial data value... | 07/24/2007 |
| 7245517 | Ferroelectric random access memory Four memory cells each obtained by connecting a ferroelectric capacitor in parallel to a transistor are connected in series with each other to constitute a cell block. A sense amplifier circuit is arranged on a one-end side in a column direction every four cell bloc... | 07/17/2007 |
| 7245543 | Data read circuit for use in a semiconductor memory and a method therefor A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying ... | 07/17/2007 |
| 7245542 | Memory device having open bit line cell structure using burn-in testing scheme and method therefor A memory device having an open bit line cell structure uses a wafer burn-in testing scheme and a method for testing the same. The memory device includes a sense amplifier having first and second input terminals; a bit line connected to the first input terminal of th... | 07/17/2007 |
| 7245553 | Memory system and method for strobing data, command and address signals A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory de... | 07/17/2007 |
| 7245550 | Memory array decoder An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder i... | 07/17/2007 |
| 7245549 | Semiconductor memory device and method of controlling the semiconductor memory device A semiconductor memory device is provided that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared... | 07/17/2007 |
| 7242609 | Methods and apparatus for low power SRAM Methods and apparatus provide for pre-charging a bit line and a complementary bit line of an SRAM memory cell of the SRAM memory to a voltage level below a power supply level, Vdd, of the SRAM memory prior to writing data to the memory cell. ... | 07/10/2007 |
| 7243276 | Method for performing a burn-in test A DDR DRAM having a test mode and an operational mode and a method for testing the DDR DRAM. The method includes in the order recited: (a) placing the DDR DRAM in test mode; (b) issuing a band activate command to select and bring up a wordline selected for write of ... | 07/10/2007 |
| 7242600 | Circuit and method for subdividing a CAMRAM bank by controlling a virtual ground A CAM bank is functionally divided into two or more sub-banks, without replicating CAM driver circuits, by disabling all match line discharge circuits in the bank, and selectively enabling the discharge circuits in entries comprising sub-banks. At least one selectiv... | 07/10/2007 |
| 7242627 | Semiconductor device The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sens... | 07/10/2007 |
| 7242603 | Method of operating a complementary bit resistance memory sensor The present invention relates to a method and apparatus for sensing the resistance state of a programmable resistance memory, using complementary memory elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A... | 07/10/2007 |
| 7242620 | Nonvolatile semiconductor memory device and an operation method thereof A nonvolatile semiconductor memory device comprises a memory cell array which a plurality of an electrically rewritable nonvolatile memory cell is arranged and a sense amplifier having first, second and third circuits holding write-in data; and the first circuit rec... | 07/10/2007 |
| 7242626 | Method and apparatus for low voltage write in a static random access memory An integrated circuit memory includes a plurality of memory cells, where each of the plurality of memory cells comprises a first storage node and a second storage node. Each of the plurality of memory cells comprises a transistor coupled between the first and second... | 07/10/2007 |
