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| Number | Title | Issue Date |
| 8179735 | Using differential signals to read data on a single-end port In some embodiments related to reading data in a memory cell, the data is driven to a local bit line, which drives a local sense amplifier. Depending on the logic level of the data in the memory cell and thus the local bit line, the local sense amplifier transfers t... | 05/15/2012 |
| 8174917 | Semiconductor memory for disconnecting a bit line from sense amplifier in a standby period and memory system including the semiconductor memory Each memory block has a plurality of memory cells, and word lines and bit lines connected to the memory cells. Precharge switches connect the bit lines to a precharge line. A switch control circuit controls an operation of the precharge switches and sets a cutoff fu... | 05/08/2012 |
| 8174916 | Bit line precharge circuit and a semiconductor memory apparatus using the same A bit line precharge circuit includes a precharge signal generation unit configured to generate first and second precharge signals that are enabled at different timing points by receiving a bit line equalizing signal; a first precharge unit configured to connect a p... | 05/08/2012 |
| 8174918 | Passgate for dynamic circuitry A dynamic circuit utilizing a passgate on a bit line is disclosed. In one embodiment, a precharge circuit is coupled to a first bit line, while a discharge circuit is coupled to a second bit line. A passgate transistor is coupled between the first bit line and the s... | 05/08/2012 |
| 8174919 | Apparatus and method for increasing data line noise tolerance Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage, either by providing a higher data line charge voltage with a voltage source, or by providing a higher data l... | 05/08/2012 |
| 8164934 | Content addressable memory An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but ... | 04/24/2012 |
| 8154937 | Auto-precharge signal generator An auto-precharge signal generation circuit comprises a signal generator, a set signal generator, and an auto-precharge signal generator. The signal generator is configured to generating a control signal and a precharge control signal in response to receiving a firs... | 04/10/2012 |
| 8144536 | Semiconductor memory and system A word driver supplies a high level voltage to a word line when a memory cell is accessed and supplies low level voltage which is a negative voltage to the word line when the memory cell isn't accessed. A precharge circuit lowers a precharge voltage-supplying capaci... | 03/27/2012 |
| 8144537 | Balanced sense amplifier for single ended bitline memory architecture A balanced differential amplifier sense amplifier senses the voltage level in a selected single bit line memory cell. The output of the selected single bit-line memory cell is connected to one input of the balanced differential sense amplifier while the other input ... | 03/27/2012 |
| 8130578 | High integrated open bit line structure semiconductor memory device with precharge units to reduce interference or noise A semiconductor memory device, having a 6F2 open bit line structure, connects each bit line of a bit line pair to a respective bit line of a neighboring bit line pair for a precharge operation so that a layout size of the semiconductor memory device decreases. Plura... | 03/06/2012 |
| 8130579 | Memory device and method of operation thereof Memory devices and methods of operating a memory cell are disclosed in which a bitline can be grounded after charge sharing with an electrically floating ground line and before writing data to the memory cell. An electric potential of an upper power supply node of a... | 03/06/2012 |
| 8130576 | Memory throughput increase via fine granularity of precharge management Methods and apparatus to improve throughput in memory devices are described. In one embodiment, memory throughput is increased via fine granularity of precharge management. In an embodiment, three separate precharge timings may be used, e.g., optimized per memory ba... | 03/06/2012 |
| 8130577 | Semiconductor memory device A semiconductor memory device includes a sub memory cell array region having memory cells each connected between word lines extending in a first direction and bit lines extending in a second direction that is orthogonal to the first direction of extension of the wor... | 03/06/2012 |
| 8125845 | Semiconductor integrated circuit device and operating method thereof Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-l... | 02/28/2012 |
| 8125844 | Semiconductor memory device for low voltage A semiconductor memory device includes a first cell array including a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells. Each unit cell is provided with a PMOS transistor and a capacitor. Th... | 02/28/2012 |
| 8120978 | Semiconductor memory device having auto-precharge function To provide a semiconductor memory device including: a first clock generation circuit and a second clock generation circuit that generate a first internal clock and a second internal clock, respectively; a latency counter that counts latency synchronously with the fi... | 02/21/2012 |
| 8102725 | Method for controlling a pre-charge process and a respective integrated circuit A method of controlling a pre-charge process of a data line (21, 22) in an integrated circuit (100) comprises the step of monitoring a rate of change of a voltage applied to the data line (21, 22) for enhancing the security. Further a respective... | 01/24/2012 |
| 8089794 | Precharge circuits and methods for content addressable memory (CAM) and related devices A method may include selectively coupling a result line to a reference node in response to a compare data value being applied to a plurality of compare cell circuits; precharging the result line to the precharge potential by enabling a first precharge path while the... | 01/03/2012 |
| 8077533 | Memory and method for sensing data in a memory using complementary sensing scheme In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118 | 12/13/2011 |
| 8050124 | Semiconductor memory device and method with two sense amplifiers A semiconductor memory device includes: plural bit lines connected with plural memory cells, respectively; plural transfer lines allocated in common to the plural bit lines; sense amplifiers (SA1) and (SA2) connected to these transfer lines, respective... | 11/01/2011 |
| 8040747 | Circuit and method for controlling precharge in semiconductor memory apparatus A circuit for controlling precharge in a semiconductor memory apparatus includes a read clock driver configured to drive an internal clock signal and generate a read burst clock signal; a read precharge control unit configured to generate a read auto precharge signa... | 10/18/2011 |
| 8040746 | Efficient word lines, bit line and precharge tracking in self-timed memory device A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line col... | 10/18/2011 |
| 8036056 | Semiconductor memory device and method of inputting and outputting data in the semiconductor memory device A semiconductor memory device includes a memory cell array and an input/output path circuit. The input/output path circuit performs an input/output line pre-charge operation at a write end time point and outputs data stored in the memory cell array when the semicond... | 10/11/2011 |
| 8031545 | Low read current architecture for memory A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured. ... | 10/04/2011 |
| 8027213 | Mechanism for measuring read current variability of SRAM cells A mechanism for measuring the variability of the read current of SRAM cells on an integrated circuit includes the integrated circuit having an SRAM array including a plurality of SRAM cells. The integrated circuit may also include a selection circuit configured to s... | 09/27/2011 |
| 8027212 | Method and apparatus for a dynamic semiconductor memory with compact sense amplifier circuit A high-density dynamic memory device with compact sense amplifier circuit is described. The memory device achieves high density through the use of a compact sense amplifier circuit that employs a single transistor to sense stored dynamic data. Functionality of the d... | 09/27/2011 |
| 8009494 | Semiconductor memory device implementing full-VDD bit line precharge scheme using bit line sense amplifier A semiconductor memory device using a full-VDD bit line precharge scheme by using a bit line sense amplifier includes a precharge unit precharging a bit line and a complementary bit line from a power voltage to a voltage that is less than the power voltage by a pred... | 08/30/2011 |
| 8009495 | Memories with front end precharge Methods, apparatuses and systems of operating digital memory where the digital memory device including a plurality of memory cells receives a command to perform an operation on a set of memory cells, where the set of memory cells contains fewer memory cells than the... | 08/30/2011 |
| 8004916 | Semiconductor circuit Embodiments relate to semiconductor devices and methods for fabricating semiconductor devices. According to embodiments, a semiconductor device may include a bit line and a bit line bar. The device may also include a precharge controller that may generate a precharg... | 08/23/2011 |
| 7995410 | Leakage and NBTI reduction technique for memory In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and partic... | 08/09/2011 |
| 7995409 | Memory with independent access and precharge Digital memory devices and systems, as well as methods of operating digital memory devices, that include access circuitry to access a first subset of a plurality of memory cells associated with a current access address during a current access cycle and precharge cir... | 08/09/2011 |
| 7986571 | Low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being ac... | 07/26/2011 |
| 7986577 | Precharge voltage supplying circuit A precharge voltage supplying circuit comprises a control signal generating unit for generating a first control signal in response to a power-up signal and a clock enable signal, and a precharge voltage control unit having a bleeder circuit and driving the bleeder c... | 07/26/2011 |
| 7983102 | Data detecting apparatus and methods thereof A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of mem... | 07/19/2011 |
| 7978551 | Bit line equalizing control circuit of a semiconductor memory apparatus A bit line equalizing control circuit of a semiconductor memory apparatus includes a control signal generating unit that receives a bank active signal to generate a control signal such that a bit line equalizing signal is delayed and enabled, a bit line equalizing s... | 07/12/2011 |
| 7965570 | Precharge control circuits and methods for memory having buffered write commands Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at least one bank of memory. One such control circuit includes at least one precharge preprocessor circuit.... | 06/21/2011 |
| 7965569 | Semiconductor storage device A voltage of a bit line connected to a memory cell is stepped up up to a power supply voltage by a precharge circuit. Before data is read from the memory cell, the voltage of the bit line is stepped down to a voltage level lower than the power supply voltage by a st... | 06/21/2011 |
| 7952946 | No-disturb bit line write for improving speed of eDRAM A method of operating a memory circuit includes providing the memory circuit. The memory circuit includes a memory cell; a word line connected to the memory cell; a first local bit line and a second local bit line connected to the memory cell; and a first global bit... | 05/31/2011 |
| 7948820 | Circuit pre-charge to sense a memory line Commonly, read times of a memory line are slowed due to voltage overshoot and/or voltage undershoot. To eliminate these problems, a control component can manage voltage while a leakage component manages timing of voltage. This allows for a line pre-charge that produ... | 05/24/2011 |
| 7940589 | Bit line sense amplifier of semiconductor memory device and control method thereof A bit line sense amplifier circuit for use in a semiconductor memory device, and a control method thereof, in which the bit line sense amplifier circuit is controlled to maintain a precharge state thereof until a sense amplifier enable signal to enable the sense amp... | 05/10/2011 |
