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| Number | Title | Issue Date |
| 8130556 | Pair bit line programming to improve boost voltage clamping A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pair... | 03/06/2012 |
| 8094509 | Apparatus and method for placement of boosting cell with adaptive booster scheme A memory includes memory arrays and boost converter circuitry. The boost converter circuitry provides at least one boosted voltage to each of the memory arrays when the memory array is being accessed. The boosted voltages may include a word line voltage, and/or a pa... | 01/10/2012 |
| 8000161 | Method and system for encoding to eliminate parasitics in crossbar array memories A method of encoding data stored in a crossbar memory array, such as a nanowire crossbar memory array, to enable significant increases in memory size, modifies data words to have equal numbers of ‘1’ bits and ‘0’ bits, and stores the modified words together ... | 08/16/2011 |
| 7986576 | Digit line equilibration using access devices at the edge of sub-arrays A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a first digit line to an equilibration reference and coupl... | 07/26/2011 |
| 7948819 | Integrated circuit having a memory with process-voltage-temperature control Certain embodiments of the inventions provide an integrated circuit (IC) having a processor operatively coupled to a PVT (process-voltage-temperature) source and an adjustable memory. The processor receives from the source an input characterizing the present PVT con... | 05/24/2011 |
| 7826288 | Device threshold calibration through state dependent burn-in In a method for reducing and/or eliminating mismatch in one or more devices that require a balanced state (e.g., in cross-coupled transistors in each memory cell and/or sense amp in a memory array), the bias (i.e., the preferred state) of each of the devices is dete... | 11/02/2010 |
| 7813196 | Integrated semiconductor memory and method for operating a data path in a semiconductor memory An integrated semiconductor memory contains a multiplicity of bit line pairs which each comprise a first bit line and a second bit line. Sense amplifiers are each coupled to one of the bit line pairs for evaluating a signal on the first and second bit lines. A data ... | 10/12/2010 |
| 7800965 | Digit line equilibration using access devices at the edge of sub-arrays A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a first digit line to an equilibration reference and coupl... | 09/21/2010 |
| 7729150 | High-speed and low-power differential non-volatile content addressable memory cell and array A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or... | 06/01/2010 |
| 7684270 | Equalizer circuit and method of controlling the same In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage havi... | 03/23/2010 |
| 7609570 | Switched capacitor charge sharing technique for integrated circuit devices enabling signal generation of disparate selected signal values A switched capacitor charge sharing technique for integrated circuit devices which allows for efficient charge sharing and signal level generation of exact desired values, and wherein the signal levels of the circuits sharing the charge do not have to have the same ... | 10/27/2009 |
| 7606088 | Sense amplifier circuit The disclosed embodiments relate to an equalization circuit, which may include a first sense amplifier having an input, the input being electrically isolated from an input to a second sense amplifier. An equalizer may be connected to the input to the first sense amp... | 10/20/2009 |
| 7502273 | Two-port SRAM with a high speed sensing scheme A static random access memory (SRAM) macro includes: a cell array having one or more SRAM cells addressed by a plurality of bit lines and word lines; one or more reference cells coupled to at least one reference bit line and the word lines addressing the SRAM cells;... | 03/10/2009 |
| 7460423 | Hierarchical 2T-DRAM with self-timed sensing An embodiment of the present invention is an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit l... | 12/02/2008 |
| 7443750 | Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorb... | 10/28/2008 |
| 7443749 | Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorb... | 10/28/2008 |
| 7440309 | Memory having parity error correction A memory includes a sense amplifier segment and a plurality of word lines including a spare word line, a first transfer word line, and a second transfer word line complementary to the first transfer word line. The memory includes a plurality of bit lines coupled to ... | 10/21/2008 |
| 7436696 | Read-preferred SRAM cell design A read-preferred SRAM cell includes a pull-up MOS device having a first drive current, a pull-down MOS device coupled to the pull-up MOS device, the pull-down MOS device having a second drive current, and a pass-gate MOS device having a third drive current coupled t... | 10/14/2008 |
| 7436720 | Semiconductor memory device A semiconductor memory device includes plates accessed by different row addresses and a sense amplifier column between the adjacent plates. The sense amplifier column is a mixture of configurations, one in which one of the pair of bit lines is twisted, and another i... | 10/14/2008 |
| 7433250 | Sense amplifier circuit An equalization circuit may include a first sense amplifier having an input, the input being electrically isolated from an input to a second sense amplifier. An equalizer may be connected to the input to the first sense amplifier to provide an equalizing voltage to ... | 10/07/2008 |
| 7423923 | Capacitor supported precharging of memory digit lines Circuits and methods are provided for precharging pairs of many digit lines. The final precharge voltage of the digit lines is different from the average of the digit line voltages prior to precharging. The final precharge voltage can be set by appropriately selecti... | 09/09/2008 |
| 7423895 | High-speed and low-power differential non-volatile content addressable memory cell and array A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or... | 09/09/2008 |
| 7414896 | Technique to suppress bitline leakage current Methods and apparatus that may help reduce standby current in memory devices are provided. By separating equalizing and precharging functions into separate circuit structures, current paths between a source of precharge voltage and a defective wordline (e.g., having... | 08/19/2008 |
| 7405470 | Adaptable electronic storage apparatus A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semicon... | 07/29/2008 |
| 7403439 | Bitline leakage limiting with improved voltage regulation Circuit arrangements and methods are provided for regulating and maintaining voltage on bitlines of a semiconductor memory device. According to one embodiment, first and second regulation devices are connected to a charging circuit. At the beginning of a charging pe... | 07/22/2008 |
| 7394701 | Circuit and method of driving a word line by changing the capacitance of a clamp capacitor to compensate for a fluctuation of a power supply voltage level A word line driving circuit includes a read voltage generator and a word line driver. The read voltage generator precharges a clamp capacitor with a power supply voltage to stably generate a read voltage in response to a read command. A capacitance of the clamp capa... | 07/01/2008 |
| 7385865 | Memory circuit In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line. ... | 06/10/2008 |
| 7376027 | DRAM concurrent writing and sensing scheme This invention discloses a write-sensing circuit for semiconductor memories comprising a first and a second local bit-lines (BLs) forming a complementary BL pair, a first and a second global bit-lines (GBLs) forming a complementary GBL pair, and at least one switchi... | 05/20/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7369450 | Nonvolatile memory having latching sense amplifier and method of operation A memory comprises a sense amplifier for sensing a logic state of a selected bitline. The sense amplifier includes a first precharge circuit, a current-to-voltage converter, a latch circuit, and a second precharge circuit. The first precharge circuit is for precharg... | 05/06/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7362624 | Transistor level shifter circuit A transistor level shifter circuit constituted by a plurality of PMOS TFT is included. The transistor level shifter circuit primarily includes a conversion circuit, a first amplifier circuit, and a second amplifier circuit. With the simplified circuit arrangement an... | 04/22/2008 |
| 7359239 | Non-volatile memory device having uniform programming speed Flash memory devices having a cell string structure. According to the present invention, the size of a first group of memory cells connected to a first word line and a second group of memory cells connected to a last word line is formed greater than that of a third ... | 04/15/2008 |
| 7359266 | Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit l... | 04/15/2008 |
| 7355881 | Memory array with global bitline domino read/write scheme A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells i... | 04/08/2008 |
| 7349264 | Alternate sensing techniques for non-volatile memories The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing ... | 03/25/2008 |
| 7349231 | Semiconductor memory device There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the compa... | 03/25/2008 |
| 7348209 | Resistance variable memory device and method of fabrication Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a resistance variable memory device is provided having at least one tin-chalcogenide layer proximate at least on... | 03/25/2008 |
| 7348653 | Resistive memory cell, method for forming the same and resistive memory array using the same A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly pa... | 03/25/2008 |
| 7349273 | Access circuit and method for allowing external test voltage to be applied to isolated wells An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective well... | 03/25/2008 |
