Class 365/201 - Testing

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter including the specifics of the memory which
No. of patents: 4260
Last issue date: 05/29/2012

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Number	Title	Issue Date
7403437	ROM test method and ROM test circuit The present invention provides a ROM test circuit capable of shortening a test time and a test method therefor. When data written into a plurality of ROMs are tested, data of the ROM(1) and ROM(2) are selected based on the output data of the specific R...	07/22/2008
7403438	Memory array architecture and method for high-speed distribution measurements A method includes an initial process of selecting a memory cell within the memory array and an operating condition under which the memory cell is to be tested. The memory cell is tested under the specified operating condition, and a measured response obtained theref...	07/22/2008
7403417	Non-volatile semiconductor memory device and method for operating a non-volatile memory device Embodiments of the invention relate to non-volatile memory devices and their methods of manufacture. Embodiments comprise an array of non-volatile memory cells, the array comprising a multiplicity of array columns having at least one redundant column of non-volatile...	07/22/2008
7400543	Metal programmable self-timed memories A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing sig...	07/15/2008
7401281	Remote BIST high speed test and redundancy calculation Disclosed is a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a ...	07/15/2008
7397692	High performance single event upset hardened SRAM cell An SRAM cell. The SRAM cell includes a first CMOS inverter and a second CMOS inverter, an input of the first inverter connected to an output of the second inverter and an input of the second inverter connected to an output of the first inverter, a first MOSFET inter...	07/08/2008
7397709	Method and apparatus for in-system redundant array repair on integrated circuits Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit wit...	07/08/2008
7397715	Semiconductor memory device for testing redundancy cells Provided is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including regular cells; a redundancy memory cell array including redundancy cells for substituting for defective regular cells; a command decoder for generating...	07/08/2008
7394708	Adjustable global tap voltage to improve memory cell yield A system that increases device yield by correcting improper operation of the device's memory cells due to process variations is disclosed. The device includes an array of memory cells and an adjustable bias voltage circuit, and is coupled to a test circuit that gene...	07/01/2008
7395464	Memory circuit having a controllable output drive A memory circuit having a controllable output drive includes a storage circuit configured for at least temporarily storing a logical state of the memory circuit, and a drive control circuit coupled to the storage circuit. The drive control circuit is configurable fo...	07/01/2008
7395466	Method and apparatus to adjust voltage for storage location reliability According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storag...	07/01/2008
7395476	System, method and storage medium for providing a high speed test interface to a memory subsystem A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high speed bus. The high speed bus operates at a faster speed than the slow sp...	07/01/2008
7395475	Circuit and method for fuse disposing in a semiconductor memory device A fuse disposing circuit executes a same test as in a state before a fuse is cut, even in case the fuse is cut. For this, the fuse disposing circuit in accordance with the invention includes a test mode enable confirmation section for informing whether a test mode i...	07/01/2008
7392444	Non-volatile memory evaluating method and non-volatile memory The present method generates a greater number of hot holes than those generated by normal write/erase operations, thereby making it possible to evaluate an operation of a non-volatile memory with respect to hot holes. The present method performs a write operation to...	06/24/2008
7392457	Memory storage device having a nonvolatile memory and memory controller with error check operation mode A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correc...	06/24/2008
7391663	Structure and method for measuring the channel boosting voltage of NAND flash memory at a node between drain/source select transistor and adjacent flash memory cell Provided is a structure for testing a NAND flash memory including a string select transistor, a source select transistor, flash memory cells connected in series between the string select transistor and a source select transistor and a measurement pad coupled to a no...	06/24/2008
7392443	Method and apparatus for testing DRAM memory chips in multichip memory modules Method and apparatus for testing memory cells of a DRAM memory chip arranged together with a nonvolatile memory chip in a multichip memory module. The multichip memory module may be incorporated in an application apparatus, in particular in a mobile telephone or a n...	06/24/2008
7391658	Internal voltage generator capable of regulating an internal voltage of a semiconductor memory device An internal voltage generator maintains stable level of an internal voltage without increasing physical area. The internal voltage generator includes an active level detector for detecting a level of an internal voltage by comparing the level of the internal voltage...	06/24/2008
7391662	Semiconductor memory device with redundancy circuit A semiconductor device has a memory cell, decoders, a redundancy circuit and a mode setting circuit. The memory cell array has word lines including a redundant word line, bit lines and memory cells. A row decoder selects the word lines in response to a row address. ...	06/24/2008
7388796	Method for testing memory under worse-than-normal conditions A method for testing a memory with cell plates and bit-line plates comprises putting the memory in a test mode, applying a test pattern to the memory, then providing a first voltage higher than Vdd/2 to the cell plate when writing a ‘1’ to a predetermined cell, ...	06/17/2008
7388797	Semiconductor memory device An apparatus for detecting a defect of a data transfer line in a semiconductor memory device, including a data transfer unit for transferring data between a local I/O line and a global I/O line; a data transfer controller for controlling the data transfer unit by ge...	06/17/2008
7388393	Semiconductor test apparatus A semiconductor test apparatus is provided that has a function for picking a device as a non-defective device with a limited function (i.e., class B device) even if that device includes one or more defective cells satisfying a predetermined condition. In order to ac...	06/17/2008
7388793	Method for configuring a voltage regulator A voltage regulator connected to a memory cell is configured by identifying at least a first and a second operation regions of the cell and associating the first and second operation regions with respective first and second operation conditions of the memory cell. A...	06/17/2008
7389459	Provision of debug via a separate ring bus in a data processing apparatus A data processing apparatus is provided having a plurality of functional units. At least one of the functional units is operable to perform data processing operations and at least a subset of the plurality of functional units have at least one of a respective co-pro...	06/17/2008
7385864	SRAM static noise margin test structure suitable for on chip parametric measurements A set of memory cell test structures and a method for assessing of the static noise margin (SNM) of a memory cell or cells, using discrete point measurement structures provided either on-chip or within the scribe lines. A set of memory structures may comprise first ...	06/10/2008
7386769	On chip diagnosis block with mixed redundancy On chip diagnosis method and on chip diagnosis block with mixed redundancy (IO redundancy and word-register redundancy) is provided. During a BIST (Built-In Self Test), information needed to apply redundancy resources is stored inside two arrays (fill_array, shift_a...	06/10/2008
7382669	Semiconductor memory component and method for testing semiconductor memory components A semiconductor component and method of testing a semiconductor component is disclosed. The invention relates to the parallel testing of semiconductor memory components having a fully functional memory area, which are classified as all good memory, and of semiconduc...	06/03/2008
7382670	Semiconductor integrated circuit device There is disclosed a semiconductor integrated circuit device having first and second load circuits for write. At the time of an all bit-stress test, a high voltage for write is supplied from the first and second load circuits for write to the all bit lines. At the t...	06/03/2008
7382671	Method for detecting column fail by controlling sense amplifier of memory device Disclosed is a method for detecting a column fail by controlling a sense amplifier of a memory device. The method includes the steps of enabling a word line of a memory cell of the memory device, adjusting a timing of a high-level driving voltage and a low-level dri...	06/03/2008
7382674	Static random access memory (SRAM) with clamped source potential in standby mode A semiconductor memory device includes a memory cell array including a plurality of memory cells, a source terminal which supplies a source potential to the memory cells, a first switching element which electrically connects the source terminal and a first power sup...	06/03/2008
7382668	Full-stress testable memory device having an open bit line architecture and method of testing the same A full-stress testable memory device having an open bit line architecture and a method of testing the memory device. The memory device of the invention includes dummy bit lines, and a voltage controller connected to the dummy bit lines. The voltage controller altern...	06/03/2008
7379349	Simultaneous and selective memory macro testing A semiconductor device includes: a plurality of memory macros, each of which includes a plurality of memory cells, is activated in accordance with a corresponding active macro selection signal, and operates in an active mode according to a corresponding active mode ...	05/27/2008
7379361	Fully-buffered memory-module with redundant memory buffer in serializing advanced-memory buffer (AMB) for repairing DRAM A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets o...	05/27/2008
7380198	System and method for detecting write errors in a storage device A system for detecting write errors in a storage device is disclosed. The system comprises a storage device; within the storage device, means for storing one or more data blocks in a storage group, the storage group comprising the one or more data blocks and a check...	05/27/2008
7378863	Synchronous semiconductor device, and inspection system and method for the same The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress t...	05/27/2008
7379339	Device and procedure for measuring memory cell currents The invention relates to a procedure and a device for measuring memory cell currents, in particular for non-volatile memory components, where the device has a current mirroring device for mirroring a current flowing through a memory cell when it is being read, and d...	05/27/2008
7376889	Memory device capable of detecting its failure A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data inp...	05/20/2008
7376026	Integrated semiconductor memory having sense amplifiers selectively activated at different timing An integrated semiconductor memory includes a memory cell array in which first sense amplifiers are arranged on a right-hand side of the memory cell array and second sense amplifiers are arranged on a left-hand side of the memory cell array. Due to “post-sense cou...	05/20/2008
7376036	Semiconductor device including fuse and method for testing the same capable of suppressing erroneous determination In a method for testing whether or not a fuse on a semiconductor substrate is disconnected, a first test operation is performed upon the fuse by determining whether or not a resistance value of the fuse is larger than a first threshold resistance value. Then, a seco...	05/20/2008
7372749	Methods for repairing and for operating a memory component In a method for repairing a memory component, data retention times of regular memory cells are determined. Weak regular memory cells having a data retention time that is shorter than a predetermined limit value are determined. A device is programmed in such a manner...	05/13/2008

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Class 365/201 - Testing