Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
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| Number | Title | Issue Date |
| 7362622 | System for determining a reference level and evaluating a signal on the basis of the reference level A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for evaluating the signal on the basis of the reference level. ... | 04/22/2008 |
| 7362631 | Semiconductor memory device capable of controlling drivability of overdriver A semiconductor memory device capable of controlling a drivability of an overdriver is provided. The semiconductor memory device includes: a first power supply for supplying a normal driving voltage; a memory cell array block; a bit line sense amplifier block for se... | 04/22/2008 |
| 7362159 | Semiconductor integrated circuit There is here disclosed a semiconductor integrated circuit comprising a laser beam irradiation object having one end portion at which a first potential is applied, a first transistor has a source and a drain wherein one of the source and the drain to which the other... | 04/22/2008 |
| 7362652 | Semiconductor circuit A semiconductor circuit which includes one or plural fuse circuits being disconnectable and having a connected or disconnected state and a control circuit controlling a controlled circuit is provided. The control circuit controls the controlled circuit according to ... | 04/22/2008 |
| 7363554 | Method of detecting errors in a priority encoder and a content addressable memory adopting the same A method of detecting errors in a priority encoder and a content addressable memory (CAM) adopting the same are provided. The CAM includes a CAM cell array, a priority encoder, and a shift register unit. The priority encoder tests the CAM cell array to determine if ... | 04/22/2008 |
| 7362632 | Test parallelism increase by tester controllable switching of chip select groups Embodiments of the invention generally provide methods and systems for increasing the level of parallelism in testing memory devices. A set of test signals provided by a memory tester may be shared by two or more devices under test. A chip selector may be used to se... | 04/22/2008 |
| 7362641 | Method and system for low power refresh of dynamic random access memories A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memo... | 04/22/2008 |
| 7362697 | Self-healing chip-to-chip interface A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path i... | 04/22/2008 |
| 7363419 | Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is dire... | 04/22/2008 |
| 7362634 | Built-in system and method for testing integrated circuit timing parameters A built-in self-test system for a dynamic random access memory device using a data output register of the memory device to apply test signals to data bus terminals and a data strobe terminal of the memory device responsive to respective clock signals. The clock sign... | 04/22/2008 |
| 7363556 | Testing apparatus and testing method A testing apparatus for testing a memory-under-test includes a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test and a fail memory unit for storing the test result of said memory-under-test. The fail... | 04/22/2008 |
| 7362635 | Semiconductor memory device A semiconductor memory device includes a control signal generator for combining command signals applied from an external portion to generate a test signal; a set/reset signal generator for receiving a mode setting signal applied from an external portion in response ... | 04/22/2008 |
| 7362633 | Parallel read for front end compression mode Methods and apparatus for increasing front-end testing throughput by allowing simultaneous access to multiple banks are provided. Techniques described herein take advantage of the reduced number of data lines required for transmitting compressed test data. Data line... | 04/22/2008 |
| 7360129 | Simultaneous switch test mode The present invention provides a simultaneous switching (SS) test mode. SS test modules supporting an SS test mode are provided. When SS test mode is enabled, SS test mode data is driven on a data bus during an idle bus period. Otherwise, when SS test mode is disabl... | 04/15/2008 |
| 7360134 | Centralized BIST engine for testing on-chip memory structures One embodiment of the present invention provides a system that uses a single built-in-self-test (BIST) engine to test multiple on-chip memory structures. During chip-test or power-on-self-test in the system, the BIST engine tests multiple on-chip memory structures w... | 04/15/2008 |
| 7360128 | Method of testing memory device A test method of a memory device equipped with an internal signal generating circuit which generates an internal signal with a fixed cycle asynchronous with a signal from the outside is disclosed in which when an entry information is input, an entry circuit generate... | 04/15/2008 |
| 7359268 | Semiconductor memory device for low voltage A semiconductor memory device includes a read amplifying unit for transferring a data from a local data line pair to a global data line as a read data; a write driver for transferring a write data from the global data line to the local data line pair; and an input/o... | 04/15/2008 |
| 7360116 | Built-in self test circuit A built-in self test circuit (BIST circuit) in an LSI includes a verification test pattern generator for generating verification test pattern which is used for verifying the connections in the LSI including the BIST circuit in the design stage thereof, and another t... | 04/15/2008 |
| 7359260 | Repair of memory cells A memory device has at least one sub array of memory cells having data columns and at least one spare sub array having spare columns. In one embodiment the sub array of memory cells and the sub array having spare columns are the same sub array. Individual elements i... | 04/15/2008 |
| 7359261 | Memory repair system and method An IC includes a memory module that stores at least one of data and code. A memory repair database stores data relating to defective memory addresses. A memory control module communicates with the memory module and the memory repair database, detects defective memor... | 04/15/2008 |
| 7359262 | Semiconductor memory device A semiconductor memory device according to the present invention where the entire memory area determined by an array of memory cells is divided into a plurality of memory areas comprises at least one relief memory area for redundancy relieving a fault memory area wh... | 04/15/2008 |
| 7359265 | Data flow scheme for low power DRAM Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determ... | 04/15/2008 |
| 7359275 | Reduced size dual-port SRAM cell A dual-port Static Random Access Memory (SRAM) cell is disclosed that includes a storage element that is operable to store a data bit and a complement data bit. The dual-port SRAM cell further includes read access circuitry dedicated exclusively to a read operation ... | 04/15/2008 |
| 7358797 | Semiconductor device having secure operating characteristic under low power environment Provided is a semiconductor device that can secure a current consumption characteristic and an operating speed characteristic under a low power voltage environment. The semiconductor device is divided into a plurality of regions depending on the current consumption ... | 04/15/2008 |
| 7359266 | Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit l... | 04/15/2008 |
| 7358755 | Ring oscillator system Testing devices at various locations on a die may be used to determine one or more properties of the locations. For example, a testing device including an oscillator such as a ring oscillator at a location may be used to determine a silicon quality, temperature, and... | 04/15/2008 |
| 7359278 | Method for producing an integrated memory module A method for producing an integrated memory module containing a command decoding device that responds to external operation commands to set operating states of the memory module for carrying out operations in accordance with a predetermined specification of the memo... | 04/15/2008 |
| 7359263 | Chip information managing method, chip information managing system, and chip information managing program In replacing word lines having defective addresses with redundant word lines, information is held in a relationship between the word lines and the redundant word lines. In other words, information is held in a replacement rule. With this arrangement, information suc... | 04/15/2008 |
| 7360011 | Memory hub and method for memory system performance monitoring A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics-for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, ... | 04/15/2008 |
| 7360005 | Software programmable multiple function integrated circuit module An electrically programmable multiple selectable function integrated circuit module has a plurality of optionally selectable function circuits, which receive and manipulate a plurality of input data signals. The outputs of the plurality of optionally selectable func... | 04/15/2008 |
| 7355384 | Apparatus, method, and computer program product for monitoring and controlling a microcomputer using a single existing pin A method, apparatus, and computer program product are disclosed for monitoring and controlling a device using only one input/output (I/O) communication pin of the device. The pin is configured to be used to both transmit and receive data. Logical ones are generated ... | 04/08/2008 |
| 7355911 | Semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories) A semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories is disclosed. In one embodiment, in order to test the semiconductor memory components, test data are written to the memory ... | 04/08/2008 |
| 7356746 | Embedded testing circuit for testing a dual port memory A circuit tests a memory having a cell array accessible through first and second ports, the circuit comprising an address generation circuit for generating an internal address consisting of a row selection address and a column selection address in response to an ext... | 04/08/2008 |
| 7356741 | Modular test controller with BIST circuit for testing embedded DRAM circuits A modular test controller with a built-in self-test (BIST) circuit for testing an embedded DRAM (eDRAM) circuit is provided. The test controller includes a built-in self-test (BIST) core for performing tests, the BIST core including proven testing algorithms; a sele... | 04/08/2008 |
| 7356743 | RRAM controller built in self test memory An RRAM design having linear BIST memory and rectangular BIST memory, the improvement comprising at least one of the linear BIST memory and the rectangular BIST memory formed only of flipflops and logic cells. ... | 04/08/2008 |
| 7356793 | Genie: a method for classification and graphical display of negative slack timing test failures Genie is a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups f... | 04/08/2008 |
| 7356435 | Semiconductor test apparatus and control method therefor There is provided a semiconductor test apparatus including: a first waveform generating means that generates a common pattern waveform corresponding to common information common to each of a plurality of semiconductor devices; a plurality of second waveform generati... | 04/08/2008 |
| 7355908 | Nonvolatile storage device and self-redundancy method for the same The nonvolatile storage device is made up of a memory array divided into a plurality of data-storage units and a plurality of redundancy-storage units for replacing respective failed data-storage units. A control unit detects the functionality of the data-storage un... | 04/08/2008 |
| 7355878 | Programmable logic devices optionally convertible to one time programmable devices Programmable logic devices (PLDs) that can be repeatedly erased and reprogrammed, e.g., during the testing and/or design phases, and then converted to one-time programmable (OTP) devices on a permanent basis, and methods of converting a PLD to an OTP device. In some... | 04/08/2008 |
| 7355387 | System and method for testing integrated circuit timing margins An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit includes circuitry for testing the timing margins of memory devices by determining the re... | 04/08/2008 |
