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| Number | Title | Issue Date |
| 4592052 | Method of testing bubble memory devices A method of testing bubble memory devices each having a plurality of minor loops, the method being useful for detecting defective minor loops in a short time. In this method, data to be written in and/or data to be read out is divided into and stored as a... | 05/27/1986 |
| 4586162 | Bit pattern check circuit In a bit pattern check circuit, there are provided three memory devices and a bit pattern input is divided into portions of the number same as that of the memory devices. One portion of the divided bit pattern input is stored in the first memory device. T... | 04/29/1986 |
| 4584663 | Apparatus for power-on data integrity check of inputted characters stored in volatile memory A memory data coincidence device includes a volatile read write memory connected to a main power source and auxiliary backup power source, and a keyboard for supplying data to the read write memory. The device further includes a read only memory for stori... | 04/22/1986 |
| 4580246 | Write protection circuit and method for a control register A write protection circuit for a control register includes a first logic circuit which provides a write enable signal to the control register in response to simultaneously receiving a register select signal, a write control signal and an enable signal. A ... | 04/01/1986 |
| 4575824 | Method for controlling read-out or write in of semiconductor memory device and apparatus for the same A method for controlling the readout or write-in of a semiconductor memory device, and an apparatus for the same. During the selection of memory cells in a memory cell array to readout or write in data, the steps of selecting the memory cells of a specifi... | 03/11/1986 |
| 4573146 | Testing and evaluation of a semiconductor memory containing redundant memory elements A method and apparatus is described for initiating a selected functional mode for a semiconductor memory circuit to determine the implementation of redundant elements in a semiconductor memory. The method for initiating the selected functional mode compri... | 02/25/1986 |
| 4567580 | Redundancy roll call technique A disabling circuit 71 responsive to a control signal 81 generated by applying to an IC pin 86 a signal outside the range of normal operating voltages of the device 16. The disabling circuit 71 grounds the output of are dundant address decoder such as 31 ... | 01/28/1986 |
| 4553225 | Method of testing IC memories In a method of testing IC memories, at first, predetermined data such as all "0" or all "1" is written into an IC memory at a normal-operation power-supply voltage, and the written data is read out and confirmed. Next, the power-supply voltage is lowered ... | 11/12/1985 |
| 4549101 | Circuit for generating test equalization pulse A circuit for generating an equalization pulse for test purposes uses an equalization pulse generator which generates an equalization pulse in response to receiving one or more address transition signals generated from an address transition. The address t... | 10/22/1985 |
| 4547867 | Multiple bit dynamic random-access memory A dynamic MOS random-access memory is described which includes a circuit for permitting checking of the on chip refresh counter. The memory also includes a refresh generator, the frequency of which automatically varies to compensate for temperature variat... | 10/15/1985 |
| 4541090 | Semiconductor memory device A large capacity memory is improved so as to reduce its testing time length. Memory arrays are divided into a plural number of memory blocks having common address signal lines and common input/output lines, each memory block is provided with respective co... | 09/10/1985 |
| 4527254 | Dynamic random access memory having separated VDD pads for improved burn-in A random access memory, a method of manufacturing a random access memory, and a method of testing a random access memory in which separate operating voltage terminal pads are provided for the memory cell arrays and peripheral circuits of the memory. By pr... | 07/02/1985 |
| 4521872 | Instruction storage An instruction storage for storing microinstructions or macroinstructions is disclosed. Each instruction word includes error check and correction bits to enable error correction when an error is detected, and a plurality of instructions are assembled from... | 06/04/1985 |
| 4519076 | Memory core testing system A means for testing the threshold voltage changes in a programmable and erasable floating gate memory cell by accessing directly and exclusively the cells in the core, and the amplifiers that sense the operation of the cells, so as to measure the relative... | 05/21/1985 |
| 4504929 | Dynamic semiconductor memory device A dynamic semiconductor memory device provides a selected real cell, which is connected to a first of a pair of bit lines connected to a sense amplifier, and a dummy cell which is connected to a second of the pair of bit lines so as to perform a read-out ... | 03/12/1985 |
| 4502131 | Electrically programmable memory matrix An electrically programmable memory includes a test circuit usable for detection of interaction between adjacent memory cells by easily permitting a checkerboard-pattern to be programmed into the memory.... | 02/26/1985 |
| 4502140 | GO/NO GO margin test circuit for semiconductor memory A semiconductor memory circuit (140) includes a plurality of memory cells each having an access transistor (154, 158) and a storage capacitor (162, 166). The memory cells are connected to digit lines (142, 144) each of which is split into halves each conn... | 02/26/1985 |
| 4495603 | Test system for segmented memory A semiconductor memory system is organized into a plurality of segments and is equipped with multiplexed or multifunctional pin for input/output purposes; e.g. the memory address pins, since there is a portion of each memory cycle during which the logic s... | 01/22/1985 |
| 4488267 | Integrated circuit chips with removable drivers and/or buffers The organization of a frame portion of an integrated circuit chip to include buffers and drivers as well as a power supply for testing functional elements arranged in a "framed" portion of the chip permits smaller drivers and buffers and a lower power sup... | 12/11/1984 |
| 4468759 | Testing method and apparatus for dram A method for testing an MOS, dynamic random-access memory employing full capacitance dummy cells is described. During probe testing a potential higher than the reference potential is applied to the dummy cells when reading binary zeroes from the memory an... | 08/28/1984 |
| 4464750 | Semiconductor memory device A semiconductor memory device including a plurality of memory blocks (1-1, 1-2, 1-3, 1-4) each including a plurality of memory cells (C00, C01, . . . , C31,127). When test data is transmitted from one selected memory cell ... | 08/07/1984 |
| 4460982 | Intelligent electrically programmable and electrically erasable ROM An E2 PROM is disclosed which provides automatic programming verification. Before data is written into the cells, the cells are automatically erased. The contents of the cells are checked to verify that erasing has been completed. If it has not... | 07/17/1984 |
| 4459694 | Field programmable device with circuitry for detecting poor insulation between adjacent word lines A field programmable device comprises regular word lines, regular bit lines, regular memory cells connected at the intersections of the regular word lines and the regular bit lines, at least one test word line adjacent to one of the regular bit lines, and... | 07/10/1984 |
| 4459549 | Method and apparatus for testing magnetic bubble devices by varying the components of input signals Disclosed herein is a method of testing a magnetic bubble device which guarantees allowable variation ranges for a variety of signal components of input signals applied to a magnetic bubble element when the magnetic bubble device is to be energized. A var... | 07/10/1984 |
| 4459686 | Semiconductor device A semiconductor device, such as a bipolar semiconductor memory device, includes an internal circuit and a reference signal generating circuit. The difference in potential between at least one internal signal produced by the internal circuit and a referenc... | 07/10/1984 |
| 4458338 | Circuit for checking memory cells of programmable MOS-integrated semiconductor memories Circuit arrangement for checking memory cells of programmable MOS-integrated semiconductor memories, especially non-volatile semiconductor memories of the floating-gate type, has an active programming and read mode of operation wherein all word lines of t... | 07/03/1984 |
| 4451903 | Method and device for encoding product and programming information in semiconductors A method and system for encoding key product information in semiconductors is disclosed. The invention is particularly useful in connection with byte-wide memories, but also finds application in a wide range of semiconductor devices. A plurality of read o... | 05/29/1984 |
| 4435788 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device comprising a plurality of memory cells arranged in a matrix pattern and means for sensing data stored in said memory cells, characterized in that each of said memory cells comprises a pair of symmetrical submemory... | 03/06/1984 |
| 4429388 | Field programmable device with internal dynamic test circuit A field programmable device comprising a memory cell part and a plurality of test bit rows provided along bit lines of the memory cell part and/or a plurality of test word rows provided along word lines of the memory cell part. At least one of the rows of... | 01/31/1984 |
| 4428068 | IC with built-in electrical quality control flag An integrated semiconductor circuit device is provided with a special purpose readable indicator without providing additional pins. The indicator may be utilized to store information pertinent to the operativeness of the integrated circuit. The results of... | 01/24/1984 |
| 4424581 | Logic circuit with a test capability A flip-flop circuit receives a portion of a multiple bit output from a combinational logic circuit to be tested, and feeds back a plurality of bits to comprise a portion of the multiple bit input to the combinational logic circuit. The flip-flop circuit i... | 01/03/1984 |
| 4423380 | Method of testing a memory by scanning at increasing time intervals The disclosure is of a method and system for scanning all of the cells of a dynamic memory at selected increasing time intervals. The apparatus includes first and second counters coupled to a comparator, the output of which triggers the operation of the s... | 12/27/1983 |
| 4419747 | Method and device for providing process and test information in semiconductors A method and system for encoding key process and test information in semiconductors is disclosed. The invention is particularly useful in connection with byte-wide memories, but also finds application in a wide range of semiconductor devices. A plurality ... | 12/06/1983 |
| 4418403 | Semiconductor memory cell margin test circuit A margin test circuit (10) is provided for a semiconductor memory circuit having a plurality of memory cells (16). Each of the memory cells (16) in one row of cells (16) are interconnected to a word line (14). The margin test circuit (10) further includes... | 11/29/1983 |
| 4414665 | Semiconductor memory device test apparatus A memory device under test is accessed by an address generated by a pattern generator to write therein data and to read the data out to be compared with expected data, and the comparison result is stored in the fault-address memory by the same address aft... | 11/08/1983 |
| 4409675 | Address gate for memories to protect stored data, and to simplify memory testing, and method of use thereof An address gate for a random access memory includes a pair of emitter-coupled and collector-coupled transistors, and another transistor emitter-coupled to the pair of transistors. Complimentary outputs are read at the coupled emitters of the pair of trans... | 10/11/1983 |
| 4409676 | Method and means for diagnostic testing of CCD memories Diagnostic testing of a charge coupled device is facilitated by interconnecting the reference node of the sense amplifier for each data block in the CCD device with a probe contact on the device, thereby eliminating the need for applying a microprobe to t... | 10/11/1983 |
| 4399521 | Monolithic integrated circuit In a semiconductor memory device of the type having PNPN elements for transferring checking and programming currents to a memory cell, and a trigger circuit for activating the PNPN elements at a predetermined potential, a voltage limiting circuit is provi... | 08/16/1983 |
| 4384348 | Method for testing semiconductor memory device A semiconductor memory testing device and testing method comprises an address pattern generator which successively generates an address pattern which specifies the X-Y addresses of each memory cell of a semiconductor memory device which is to be tested, a... | 05/17/1983 |
| 4380805 | Tape burn-in circuit A circuit for burning-in an integrated circuit memory receives a two state signal at a burn-in terminal (168). A clock refresh signal is provided to a refresh terminal (170) which drives a refresh counter (192). A sequence of addresses are generated by th... | 04/19/1983 |
