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| Number | Title | Issue Date |
| 7372750 | Integrated memory circuit and method for repairing a single bit error The invention relates to an integrated memory circuit having a memory cell array comprising memory cells arranged on word lines and bit lines, and having a repair circuit for repairing a single bit error in one of the memory cells, the repair circuit comprising: an ... | 05/13/2008 |
| 7372716 | Memory having CBRAM memory cells and method A memory cell arrangement has a plurality of memory cells of the CBRAM type and a programming apparatus, the memory cells being arranged along bit lines and each bit line having a programming apparatus. The invention provides for the programming apparatus to compris... | 05/13/2008 |
| 7372763 | Memory with spatially encoded data storage In some embodiments, the invention provides a chip with at least one memory circuit that comprises a majority voter circuit with first and second digitally controlled variable delay elements. The first delay element is controlled by data bits that are to be written ... | 05/13/2008 |
| 7373560 | Circuit for measuring signal delays of asynchronous inputs of synchronous elements A system measures propagation delays in any number of test circuits, each having two asynchronous inputs and an output, without using their clock inputs to re-initialize the test circuits during measurement operations. The delay between one of the test circuit's asy... | 05/13/2008 |
| 7373562 | Memory circuit comprising redundant memory areas The invention relates to a memory circuit comprising regular memory areas and redundant memory areas, redundancy circuits in each case being assigned to the redundant memory areas, each redundancy circuit having permanently settable storage elements in order, in a f... | 05/13/2008 |
| 7372720 | Methods and apparatus for decreasing soft errors and cell leakage in integrated circuit structures Methods and apparatus are provided for decreasing soft errors and cell leakage in integrated circuit structures. The structures of the invention preferably include memory cells that utilize thin-film transistors (“TFTs”) for the pull-up and pull-down transistors... | 05/13/2008 |
| 7372749 | Methods for repairing and for operating a memory component In a method for repairing a memory component, data retention times of regular memory cells are determined. Weak regular memory cells having a data retention time that is shorter than a predetermined limit value are determined. A device is programmed in such a manner... | 05/13/2008 |
| 7372732 | Pulse width converged method to control voltage threshold (Vt) distribution of a memory cell A method of operating on a plurality of non-volatile multi-level memory cells is disclosed. The memory cells have at least a first, second, third and fourth program level. Each of program levels corresponds to a different binary state and has a voltage threshold dis... | 05/13/2008 |
| 7373564 | Semiconductor memory A normal write data selection circuit operates in the normal operation mode, and thus outputs data received through external data terminals to any one of regular cell arrays selected according to an address. A test write control circuit operates in the test mode, an... | 05/13/2008 |
| 7372740 | Semiconductor memory device Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurali... | 05/13/2008 |
| 7372737 | Nonvolatile memory and method of driving the same The nonvolatile memory according to the present invention can precisely read information included in a memory transistor subject to a shift phenomenon because electrical read is performed on the memory transistor by using a reference voltage generated from a refresh... | 05/13/2008 |
| 7372752 | Test mode controller A test mode controller is capable of reducing a chip area and unnecessary current consumption by integrally constructing latch units of the two test circuits. The test mode controller includes a test control block for determining a test mode between a programmable t... | 05/13/2008 |
| 7372751 | Using redundant memory for extra features Apparatus and methods are provided. A memory device has a memory array comprising primary and redundant portions. A redundancy circuit is coupled to the memory array and is coupled to receive a command signal. The redundancy circuit is adapted to be selectively prog... | 05/13/2008 |
| 7373574 | Semiconductor testing apparatus and method of testing semiconductor A semiconductor testing apparatus, includes a test signal generating unit that generates a test signal corresponding to a test pattern to output the generated test signal to a device under test (DUT); a comparison signal generating unit that generates a comparison s... | 05/13/2008 |
| 7370238 | System, method and software for isolating dual-channel memory during diagnostics A system, method and software for isolating information handling system memory system devices are disclosed. In dual-channel double-data-rate memory system implementations, teachings of the present disclosure facilitate accurate identification of memory system devic... | 05/06/2008 |
| 7370249 | Method and apparatus for testing a memory array A technique for testing a memory array. More particularly, embodiments of the invention relate to a memory array testing architecture in which a memory array within a device under test (DUT) is able to be tested at speeds substantially similar to those under typical... | 05/06/2008 |
| 7370250 | Test patterns to insure read signal integrity for high speed DDR DRAM A test method and implementation is described to test an internal data path within a DDR DRAM during a read operation. A worse case test sequence and a compliment of the worse case test sequence is stored within memory. The test sequence and its compliment are arran... | 05/06/2008 |
| 7370260 | MRAM having error correction code circuitry and method therefor An embedded memory system (10) uses an MRAM core (12) and error correction code (ECC) corrector circuitry (20). The ECC corrector circuitry identifies soft memory bit errors which are errors primarily resulting from an MRAM bit not being correct... | 05/06/2008 |
| 7369455 | Calibration circuit of a semiconductor memory device and method of operating the same A calibration circuit for a semiconductor device and a method of driving the same. The calibration circuit includes a PRBS generator in which a data pattern is generated within an integrated circuit without receiving data from the outside, a PRBS tester that compare... | 05/06/2008 |
| 7369430 | Adaptive algorithm for MRAM manufacturing Magnetic Random Access Memory (MRAM) can be programmed and read as fast as Static Random Access Memory (SRAM) and has the non-volatile characteristics of electrically eraseable programmable read only memory (EEPROM), FLASH EEPROM or one-time-programmable (OTP) EPROM... | 05/06/2008 |
| 7369452 | Programmable cell A device having an OTP memory is disclosed. A program state of the OTP device is stored at a fuse that is connected in series between a first node and a latch. During a program mode, the first node is electrically connected to a program voltage. During a read mode, ... | 05/06/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7370166 | Secure portable storage device In one embodiment of the present invention, a secure storage system includes a removable storage device having a secure storage area for storage of secure data and a public storage area and device port for coupling the removable storage device to a host, the removab... | 05/06/2008 |
| 7370237 | Semiconductor memory device capable of accessing all memory cells A semiconductor memory device according to embodiments of the invention includes N channels for interface with an outside. During a test mode where the semiconductor memory device is tested by a tester having M channels, K ones of the N channels of the memory device... | 05/06/2008 |
| 7368931 | On-chip self test circuit and self test method for signal distortion There is provided an on-chip test circuit that is capable of measuring validity of an output signal within a chip without any external measuring device. The on-chip self test circuit implemented on the same chip as a test semiconductor device includes: a test load b... | 05/06/2008 |
| 7366965 | Semiconductor integrated circuit Test functions are expanded by adopting a self test part, and circuit scale is reduced by adding the self test part. A semiconductor integrated circuit includes a memory that includes plural memory banks and is accessed by specifying a bank address, an X address, an... | 04/29/2008 |
| 7366819 | Fast unaligned cache access system and method A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the c... | 04/29/2008 |
| 7366864 | Memory hub architecture having programmable lane widths A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled t... | 04/29/2008 |
| 7366019 | Nonvolatile memory There is provided a non-volatile memory capable of being supplied with two varieties of externally supplied voltages, stabilizing the operation thereof, at a voltage in the vicinity of a threshold voltage for switching over between the externally supplied voltages, ... | 04/29/2008 |
| 7366051 | Word line driver circuitry and methods for using the same Word line driver circuitry for selectively charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology, where a first transistor is driven by a signal, DOUT, and a second transistor is driven by a time-delayed co... | 04/29/2008 |
| 7365554 | Integrated circuit for determining a voltage An integrated circuit includes a current generator circuit with a first input terminal for applying a reference voltage and a second input terminal for applying an input voltage, which is generated internally from an externally applied supply voltage by a voltage ge... | 04/29/2008 |
| 7366876 | Efficient emulation instruction dispatch based on instruction width In one embodiment, a state machine receives a plurality of instructions from an instruction register to be processed by a digital signal processor. After receiving a single RTI, the state machine loads each of the plurality of instructions one at time and determines... | 04/29/2008 |
| 7366597 | Validating control system software variables A vehicle having a system for validating a variable signal for input to a processor-performed function. An input module receives the signal. A processor tests first and second storage locations of a memory. After testing, the processor stores the signal in the first... | 04/29/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| RE40282 | Edge transition detection circuitry for use with test mode operation of an integrated circuit memory device An integrated circuit structure and method provides for an integrated circuit device to respond to an edge transition detection (ETD) pulse in one of two ways. First, in response to the ETD pulse, the integrated circuit device exits a test mode at least temporarily ... | 04/29/2008 |
| 7366970 | Method and test device for detecting addressing errors in control units The invention relates to a method for detecting addressing errors in control devices of motor vehicles, whereby test data are input into all addressable memory cells by means of a present model, then read out and compared with the test data. ... | 04/29/2008 |
| 7366971 | Semiconductor memory having sub-party cell array error correction Disposed on both sides of a parity cell array are a first regular cell array and a sub parity generation circuit therefor, and a second regular cell array and a sub parity generation circuit therefor. The sub parity generation circuit generates sub parity data accor... | 04/29/2008 |
| 7366005 | Ferroelectric memory device and display-driving IC A ferroelectric memory device including: a first bit line which extends, from one end toward another end thereof, in a first direction; a plurality of first memory cells, which are connected to the first bit line and store predetermined data; a second bit line which... | 04/29/2008 |
| 7366008 | Radiation tolerant SRAM bit In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the... | 04/29/2008 |
| 7365565 | Programmable system on a chip for power-supply voltage and current monitoring and control A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip... | 04/29/2008 |
