Bizarre Patents
Wearable Device For Feeding and Observing Birds and Other Flying Animals
A device for feeding and observing flying animals comprising a hat, a support mounted on the hat and extending outward from the hat, and a feeder mounted on the support.
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| Number | Title | Issue Date |
| 8179731 | Storage devices with soft processing A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signa... | 05/15/2012 |
| 8159889 | Solid state disk controller apparatus A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from... | 04/17/2012 |
| 8111566 | Optimal channel design for memory devices for providing a high-speed memory interface A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communicatio... | 02/07/2012 |
| 8102724 | Setting controller VREF in a memory controller and memory device interface in a communication bus A memory device is connected through an interface to a memory controller. The controller's reference voltage is set based on a driver's impendence of the memory device during driver training. The voltage is applied to a reference resistor pair at the controller and ... | 01/24/2012 |
| 8054703 | Active termination circuit and method for controlling the impedance of external integrated circuit terminals An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of ... | 11/08/2011 |
| 8054702 | Semiconductor memory device with signal aligning circuit A signal aligning circuit includes a plurality of pads receiving input signals in parallel 1 bit by 1 bit; a first transferring unit for transferring the input signals as first signals in synchronization with a first clock signal of an internal clock, and transferri... | 11/08/2011 |
| 8036051 | Semiconductor memory device and semiconductor memory system for compensating crosstalk A semiconductor memory device and a semiconductor memory system. The semiconductor memory device includes channels configured to transmit signals from a transmitter to a receiver, and a crosstalk compensator. The crosstalk compensator may be connected between the ch... | 10/11/2011 |
| 8031543 | Memory chip having a complex termination A memory chip has a signal line and a complex impedance which is connected to the signal line for termination of the signal line. A memory having such a memory chip and a method for operating a memory chip are also described. The memory chip on the memory having a s... | 10/04/2011 |
| 8000120 | Read and match circuit for low-voltage content addressable memory A read, write, and match circuit for a low-voltage content addressable memory. A write circuit inputs signals for storing data in the memory cells, a read circuit retrieves the stored data from the memory cells, and a match circuit compares the data stored in the me... | 08/16/2011 |
| 7944763 | Semiconductor memory device for preventing mal-operation induced by misrecognizing addresses/data as commands and operating method thereof A semiconductor memory device and an operating method thereof prevent the mal-operation of the semiconductor memory device induced by misrecognizing addresses or data as commands. The semiconductor memory device includes a plurality of input pads, a data information... | 05/17/2011 |
| 7924634 | Repeater of global input/output line A repeater of a global input/output line includes a data transmitter including first and second drivers for outputting data signals of the global input/output line through different transmission routes in response to a transmission direction control signal, and a th... | 04/12/2011 |
| 7864605 | Apparatus for removing crosstalk in semiconductor memory device An apparatus for removing crosstalk in a semiconductor memory device includes pads for receiving externally provided signals, transmission lines for delivering the signals received by each of the pads to corresponding elements in the apparatus, and capacitors, coupl... | 01/04/2011 |
| 7715256 | Active termination circuit and method for controlling the impedance of external integrated circuit terminals An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of ... | 05/11/2010 |
| 7692983 | Memory system mounted directly on board and associated method The invention provides an improved memory system that addresses signal degradation due to transmission line effects. The improved memory system includes a first buffer, at least one first memory device coupled to the first buffer, and a plurality of signal traces. T... | 04/06/2010 |
| 7672179 | System and method for driving a memory circuit using a pull-up resistance for inhibiting a voltage decay on a transmission line A system, method, and computer program product are provided for driving a memory circuit. In one embodiment, the memory circuit is driven utilizing a first resistance value in a first mode of operation. Further, in a second mode of operation, the memory circuit is d... | 03/02/2010 |
| 7573760 | Integrated circuit for sampling a sequence of data packets at a data output An integrated circuit comprises a sampling circuit arranged at a data output of an operating section and operated by sampling edges, data packets appearing at the data output in response to a sequence of request commands, and a control section configured to produce ... | 08/11/2009 |
| 7489570 | Semiconductor memory device with hierarchical bit line structure A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are... | 02/10/2009 |
| 7440336 | Memory device having terminals for transferring multiple types of data A memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output au... | 10/21/2008 |
| 7436717 | Semiconductor device having mechanism capable of high-speed operation A semiconductor device comprises a memory cell block and a sense amplifier zone. A selection gate included in the sense amplifier zone is turned on for selectively coupling the memory cell block with the sense amplifier zone. Local drivers are dispersively arranged ... | 10/14/2008 |
| 7423918 | Memory device having data paths with multiple speeds A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of the multiple bi-directional data paths is configured to transfer data at another speed. The memory devic... | 09/09/2008 |
| 7417901 | Memory device having terminals for transferring multiple types of data A memory device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output ... | 08/26/2008 |
| 7400539 | Memory device having terminals for transferring multiple types of data A device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxilia... | 07/15/2008 |
| 7391637 | Semiconductor memory device with high permeability composite films to reduce noise in high speed interconnects A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating materia... | 06/24/2008 |
| 7385872 | Method and apparatus for increasing clock frequency and data rate for semiconductor devices An embodiment of the present invention receives a data signal and at least one data shift signal that facilitates adjustment of the data signal and produces a resulting data signal with a data rate greater than a data rate of the data signal. ... | 06/10/2008 |
| 7382667 | Active termination circuit and method for controlling the impedance of external integrated circuit terminals An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of ... | 06/03/2008 |
| 7379339 | Device and procedure for measuring memory cell currents The invention relates to a procedure and a device for measuring memory cell currents, in particular for non-volatile memory components, where the device has a current mirroring device for mirroring a current flowing through a memory cell when it is being read, and d... | 05/27/2008 |
| 7373090 | Modulator driver circuit with selectable on-chip termination A method and apparatus to accommodate differing output loads without sacrificing impedance matching in an optical modulator driver. ... | 05/13/2008 |
| 7359257 | Semiconductor memory module and electronic apparatus including a semiconductor memory module and method for operating thereof A semiconductor memory module (1) includes a circuit substrate (2), a first (100), a second (200), a third (300) and a fourth (400) rank of memory chips (3), a first register (10) and a second register (20 | 04/15/2008 |
| 7359259 | Method for transmission and reception of a data signal on a line pair, as well as a transmission and reception circuit for this purpose Apparatuses and methods for transmitting and receiving a data signal on a line pair having a first transmission line and a second transmission line are provided. In one embodiment, a data signal which represents the data to be transmitted by means of a sequence of f... | 04/15/2008 |
| 7349289 | Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an inp... | 03/25/2008 |
| 7342300 | Integrated circuit incorporating wire bond inductance The invention relates to the field of electronics, more particularly to the wire bonds incorporated into an integrated circuit package such as a quad flat pack, a ball grid array or hybrid style module. The present invention takes the normally undesirable wire bond ... | 03/11/2008 |
| 7343256 | Configurable voltage regulator A configurable semiconductor has a device characteristic that is controllable as a function of at least one external impedance. A measurement circuit measures an electrical characteristic of the at least one external impedance and determines a select value correspon... | 03/11/2008 |
| 7339840 | Memory system and method of accessing memory chips of a memory system A memory system and method is discussed. The memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting line... | 03/04/2008 |
| 7333373 | Charge pump for use in a semiconductor memory In an embodiment, an improved charge pump circuit is provided to control a threshold voltage increase of a charge transmission transistor during a charge transfer period, and to prevent a latch-up generation during a charge non-transfer period. A charge transmission... | 02/19/2008 |
| 7330514 | Methods and apparatus to mitigate cross-talk interference A circuit board includes a pair of interconnects configured to support conveyance of a differential mode communication signal, which comprises a balanced first signal (e.g., signal X) and corresponding second signal (e.g., signal −X) of opposite polarities. A tran... | 02/12/2008 |
| 7310257 | Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit lines by respective coupling circuits. The length of the local digit ... | 12/18/2007 |
| 7292479 | Memory device with multistage sense amplifier A memory device with a multistage sense amplifier is disclosed. According to one aspect, a memory device has a memory cell array having at least one memory cell, at least one sense amplifier. Binary data signals read out from the memory cell are amplified and evalua... | 11/06/2007 |
| 7292075 | Rail-to-rail pad driver with load independent rise and fall times A pad driver is presented that in one form is capable of driving a wide range of capacitive loads with constant rise and fall times, over a wide range of temperature and process corners. A desirable form of the pad driver is characterized by the ability to charge an... | 11/06/2007 |
| 7289378 | Reconstruction of signal timing in integrated circuits Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of devices by providing for an interface having inputs and/or outputs that are adjustably delayed. This allows ... | 10/30/2007 |
| 7283013 | Contactless IC card system In a contactless IC card system, a modulating circuit manufactured in an IC form is operable at a high power efficiency. The demodulating apparatus is configured to include: first signal output means for outputting a first output signal having a predetermined phase ... | 10/16/2007 |
