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| Number | Title | Issue Date |
| 8154936 | Single-ended bit line based storage system A single-ended bit line based storage system. The storage system includes a first set of storage cells, a second set of storage cells, a first set of reference storage cells, a second set of reference storage cells, and a differential sensing block. The memory core ... | 04/10/2012 |
| 8031542 | Low leakage ROM architecture A Read only memory (ROM) with minimum leakage includes a ROM array including a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-thre... | 10/04/2011 |
| 8031541 | Low leakage ROM architecture Read only memory (ROM) with minimum leakage is provided. The ROM includes a read only memory array. The read only memory array includes a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zer... | 10/04/2011 |
| 7903481 | Page buffer circuit, nonvolatile device including the same, and method of operating the nonvolatile memory device A page buffer circuit comprises a sense unit, a latch unit, and a bit line voltage control unit. The sense unit is configured to couple a bit line and a sense node in response to a sense control signal in response to the sense control signal. The latch unit includes... | 03/08/2011 |
| 7898881 | Semiconductor memory device and data sensing method thereof A semiconductor memory device includes first and second edge drivers configured to generate sensing control signals, a memory cell array between first and second edge drivers, and pluralities of unit sense amplifiers detecting data from the memory cell array in resp... | 03/01/2011 |
| 7826284 | Sense amplifier circuit and method for semiconductor memories with reduced current consumption A sensing circuit for a semiconductor memory, includes, a detecting amplifier including a first circuital branch is run through by a first current corresponding to the sum of a second current as a function of a comparison current and a cell current. The cell current... | 11/02/2010 |
| 7791971 | Semiconductor memory device having replica circuit A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifier... | 09/07/2010 |
| 7746710 | Data bus power-reduced semiconductor storage apparatus In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a semiconductor storage apparatus is reduced, thereby reducing the power consumption. For example, a semiconductor st... | 06/29/2010 |
| 7733718 | One-transistor type DRAM A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a... | 06/08/2010 |
| 7719905 | Semiconductor memory device A semiconductor memory device has a memory cell having a hierarchical bit line structure for large capacity even in a small cell size. The semiconductor memory device comprises a unit cell configured to read/write data, a cell data sensing unit configured to adjust ... | 05/18/2010 |
| 7692979 | Memory readout circuit and phase-change memory device In a memory readout circuit for use in a phase-change memory device comprising phase-change elements as memory cells, a sense amplifier sets readout voltage, which is applied to a selected phase-change element selected among the phase-change elements by a column sel... | 04/06/2010 |
| 7688654 | Structure for differential eFUSE sensing without reference fuses A design structure comprising a differential fuse sensing system, which includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node couple... | 03/30/2010 |
| 7609568 | Method and device for securing an integrated circuit, in particular a microprocessor card A method processes parallel electrical signals, using parallel processing circuits that process successive cycles of electrical signals according to a rule for allocating electrical signals to the processing circuits. The method comprises, between the processing cyc... | 10/27/2009 |
| 7586800 | Memory timing apparatus and associated methods A computer memory includes a primary self-timing signal path defined by a model wordline signal path and a model bitline signal pair path. The primary self-timing signal path is defined to generate and transmit a model bitline signal pair. The computer memory also i... | 09/08/2009 |
| 7577049 | Speculative sense enable tuning apparatus and associated methods A computer memory includes a sense enable control module for generating a sense enable signal for a memory core. The sense enable control module includes an active side for transmitting the sense enable signal for the memory core, and a calibration side for determin... | 08/18/2009 |
| 7558134 | Semiconductor memory device and its operation method A semiconductor memory device includes a memory-cell array, a read bit line, a write bit line, a sense amplifier, a first sense line, a second sense line, a first bit line switch, and a second bit line switch. The memory-cell array is laid out to form an array. The ... | 07/07/2009 |
| 7535784 | Semiconductor memory device having replica circuit A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifier... | 05/19/2009 |
| 7499350 | Sense amplifier enable signal generator for semiconductor memory device A semiconductor memory device includes a bit line sense amplifier, a sense amplifier enable signal generator, a power line driver, and a driver controller. The bit line sense amplifier senses and amplifies data carried on a bit line. The sense amplifier enable signa... | 03/03/2009 |
| 7499349 | Memory with resistance memory cell and evaluation circuit A memory circuit comprising a memory cell which has a resistance memory element and is connected between a ground terminal and a capacitor has a reference memory cell with a reference resistor which is connected between the ground terminal and a reference capacitor,... | 03/03/2009 |
| 7489588 | Semiconductor memory device having a main amplifier equipped with a current control circuit in a burst read operation A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two ki... | 02/10/2009 |
| 7486576 | Methods and devices for preventing data stored in memory from being read out A dynamic random access memory (DRAM) device, including a DRAM core having memory cells for storing data information, and a read protection unit, prevents data stored in the memory cells before power-off, from being read out at power-on. ... | 02/03/2009 |
| 7480194 | Data input/output (I/O) apparatus for use in a memory device A data I/O apparatus for use in a memory device. The data I/O apparatus for use in the memory device performs data transmission using the same polarity when neighbor global I/O lines have opposite polarities to reduce coupling noise generated between global I/O line... | 01/20/2009 |
| 7477555 | System and method for differential eFUSE sensing without reference fuses A differential fuse sensing system includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node c... | 01/13/2009 |
| 7450448 | Semiconductor memory device The present invention provides a semiconductor memory device adjusting a bit line over driving period according to a power supply voltage level. A semiconductor memory device for stabilizing a bit line sense amplifier (hereinafter, referred as BLSA) includes the BLS... | 11/11/2008 |
| 7443750 | Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorb... | 10/28/2008 |
| 7443757 | Non-volatile memory and method with reduced bit line crosstalk errors A memory device and a method thereof allow sensing a plurality of memory cells in parallel while minimizing errors caused by bit-line to bit-line crosstalk. Essentially, the bit line voltages of the plurality of bit line coupled to the plurality of memory cells are ... | 10/28/2008 |
| 7440312 | Memory write timing system A memory write timing system includes a modified memory bitcell including a storage device and a write/read circuit for writing/reading data to/from the storage device; and an output circuit for detecting the current state of the storage device. ... | 10/21/2008 |
| 7440345 | Data output circuit of semiconductor memory device and operation method thereof A data output circuit of a semiconductor memory device and an operation method thereof, in which global I/O lines are selectively used according to a selected output data width. The data output circuit includes an I/O sense amplifier unit that selectively senses and... | 10/21/2008 |
| 7433254 | Accelerated single-ended sensing for a memory circuit A single-ended sensing circuit is provided for use with a memory circuit including a plurality of bit lines and a plurality of memory cells connected to the bit lines. The sensing circuit includes at least one charge sharing circuit and at least one switching circui... | 10/07/2008 |
| 7428179 | Apparatus for controlling activation of semiconductor integrated circuit and controlling method of the same A circuit for controlling an active period of semiconductor memory apparatus includes: an active controller that generates active control signals for determining active periods of two or more individual banks according to whether a refresh operation is performed; an... | 09/23/2008 |
| 7417918 | Method and apparatus for configuring the operating speed of a programmable logic device through a self-timed reference circuit Method and apparatus for configuring a programmable logic device to operate at a plurality of clock frequencies comprising configurable programmable self-timed delay circuits and associated configuration software. The configurable IC clock frequencies increase devic... | 08/26/2008 |
| 7417907 | Systems and methods for resolving memory address collisions A hardware implemented method for resolving collisions of memory addresses of a memory array is provided. In this hardware implemented method, a read memory address is compared with a write memory address. If the read and write memory addresses match, write data is ... | 08/26/2008 |
| 7411861 | Integrated circuit device and electronic instrument An integrated circuit device includes a RAM block including a plurality of wordlines WL, a plurality of bitlines BL, a plurality of memory cells MC, wordline control circuit, and a data read control circuit, and a data line driver block which drives a plurality of d... | 08/12/2008 |
| 7408826 | Semiconductor memory device A semiconductor memory device that includes a memory cell array having a plurality of memory cells that are connected between a bit line pair, which transfers data to the bit line pair, a precharge circuit for precharging the bit line pair to a precharge voltage lev... | 08/05/2008 |
| 7391656 | Self-feedback control pipeline architecture for memory read path applications A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection a... | 06/24/2008 |
| 7385858 | Semiconductor integrated circuit having low power consumption with self-refresh A dynamic random access memory has logically identical circuits for providing the same logical control signals. Each set of control signals can have different electrical parameters. One circuit can be optimized for high speed performance, while another circuit can b... | 06/10/2008 |
| 7382677 | Memory device having internal voltage supply providing improved power efficiency during active mode of memory operation A internal voltage generator in a semiconductor memory device has a first and second internal voltage generators. The first internal voltage generator outputs a first signal having a first voltage level to internal circuits of the memory device during an active mode... | 06/03/2008 |
| 7379356 | Memory, integrated circuit and methods for adjusting a sense amp enable signal used therewith A memory includes at least one memory segment that includes an array of memory cells arranged in a plurality of columns, each of the plurality of columns having a corresponding bitline pair. An address decoder includes a row decoder and a column decoder that address... | 05/27/2008 |
| 7375544 | Semiconductor apparatus having logic level decision circuit and inter-semiconductor apparatus signal transmission system In a signal transmission system between a plurality of semiconductor apparatuses, a logic level decision circuit deciding a logic level of an input signal in accordance with which of two reference signals a signal level of the input signal is close to, by using two ... | 05/20/2008 |
| 7372759 | Power supply control circuit and controlling method thereof The present invention provides a power supply control circuit and a control method thereof, capable of securing an accurate operation of a GIO in a burst data transmission having a high compression rate. The power supply control circuit of a semiconductor memory dev... | 05/13/2008 |
