Class 365/195 - Inhibit

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter where an inhibit operation is used to prevent
No. of patents: 648
Last issue date: 09/20/2011

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

Number	Title	Issue Date
8023344	Data retention kill function Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command si...	09/20/2011
7978540	Extraction of a binary code based on physical parameters of an integrated circuit via programming resistors An integrated cell and method for extracting a binary value based on a value difference between two resistors values, including connection circuitry for a binary reading of the sign of the difference between the resistors, and connection circuitry for a modification...	07/12/2011
7969803	Method and apparatus for protection of non-volatile memory in presence of out-of-specification operating voltage A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully. ...	06/28/2011
7889582	Segmented write bitline system and method A memory device is provided for performing writing operations on memory cells while maintaining a stability thereof. A memory array is provided including a plurality of memory cells. Additionally, segmented write bitlines are provided for performing writing operatio...	02/15/2011
7751263	Data retention kill function Various data protection techniques are provided. In one embodiment, a method includes manufacturing a memory component of an electronic system. Manufacturing the memory component may include disposing a memory array on a substrate and coupling a control circuit to t...	07/06/2010
7715246	Mask ROM with light bit line architecture For improving performance of mask ROM, bit line is multi-divided for reducing capacitance, so that multi-stage sense amps are used for reading, wherein a local sense amp receives an output from a memory cell through the bit line, and a global sense amp receives the ...	05/11/2010
7715255	Programmable chip enable and chip address in semiconductor memory Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory pac...	05/11/2010
7577057	Circuit and method for generating write data mask signal in synchronous semiconductor memory device A circuit for generating a write data mask signal in a synchronous semiconductor memory device includes an output unit and a reset control unit. The output unit controls a write data mask operation of the synchronous semiconductor memory device, latches a write data...	08/18/2009
7564727	Apparatus and method for configurable power management A method and apparatus to facilitate low-power consumption through a configurable suspend mode of operation of a PLD, the PLD comprising an application logic block coupled to receive configuration data bits and adapted to implement a logic application in response to...	07/21/2009
7545687	Semiconductor memory device A semiconductor memory device checks a RAS timing to recognize and set an operation timing of the semiconductor memory device. The semiconductor memory device includes an input buffer, a RAS timing controller and a bank controller. The input buffer transmits a RAS t...	06/09/2009
7532524	Bitline exclusion in verification operation Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines i...	05/12/2009
7492648	Reducing leakage current in memory device using bitline isolation A method for reducing defect leakage current in a semiconductor memory device comprising a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier columns comprising a plurality of sense amplifiers, wherein there is a ...	02/17/2009
7492649	Systems and methods for improving memory reliability by selectively enabling word line signals Systems and methods for reducing instability and writability problems arising from relative variations between a memory cell voltage (Vcell) and a logic voltage (Vdd) by inhibiting assertion of word line signals that enable accesses to the memory cells when the volt...	02/17/2009
7477554	Data retention kill function A method for operating a memory device is disclosed. In one embodiment, the method includes receiving authorized operating parameters of the memory device and comparing sensed operational parameters to the authorized operating parameters. Access to data stored withi...	01/13/2009
7468924	Non-volatile memory device capable of reducing threshold voltage distribution A method for programming a flash memory device which includes a plurality of memory cells arranged in rows and columns. The method includes programming selected memory cells from among the plurality of memory cells according to loaded data bits. Data bits are read f...	12/23/2008
7447086	Selective program voltage ramp rates in non-volatile memory A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line...	11/04/2008
7440312	Memory write timing system A memory write timing system includes a modified memory bitcell including a storage device and a write/read circuit for writing/reading data to/from the storage device; and an output circuit for detecting the current state of the storage device. ...	10/21/2008
7437500	Configurable high-speed memory interface subsystem A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic rando...	10/14/2008
7433260	Memory device and print recording material receptacle providing memory device The operation code decoder 204 having received an access enable signal EN acquires and decodes the command, and sends the decoded command to the read/write controller 206. In the event that the received command is a write command, the read/write contro...	10/07/2008
7430041	Semiconductor storage apparatus A semiconductor storage apparatus according to one embodiment of the present invention, comprising: memory cells which need refresh operation; and a refresh control circuit which suspends the refresh operation when external access for reading out from or writing int...	09/30/2008
7430136	Purge operations for solid-state storage devices A storage system that comprises multiple solid-state storage devices includes a command set that enables a host system to initiate one or more types of purge operations. The supported purge operations may include an erase operation in which the storage devices are e...	09/30/2008
7428171	Non-volatile memory and method with improved sensing A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction cu...	09/23/2008
7420858	Methods and apparatus for read/write control and bit selection with false read suppression in an SRAM Methods and apparatus are provided for read/write control and bit selection with false read suppression in an SRAM. According to one aspect of the invention, a bit select circuit is provided for an SRAM. The disclosed bit select circuit includes one or more transist...	09/02/2008
7421534	Data protection for non-volatile semiconductor memory using block protection flags Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to a...	09/02/2008
7417918	Method and apparatus for configuring the operating speed of a programmable logic device through a self-timed reference circuit Method and apparatus for configuring a programmable logic device to operate at a plurality of clock frequencies comprising configurable programmable self-timed delay circuits and associated configuration software. The configurable IC clock frequencies increase devic...	08/26/2008
7414899	Method and apparatus for early write termination in a semiconductor memory A synchronous DRAM (SDRAM) terminates a write operation in response to detecting deactivation of a data strobe signal applied to it during the write operation. In one example, the SDRAM comprises a buffer circuit and an early write termination circuit. The buffer ci...	08/19/2008
7408823	Semiconductor device and method thereof A semiconductor device and method thereof. The semiconductor device may include a protection unit receiving an input signal and outputting a switching control signal based on the received input signal, the received input signal indicating an operating mode of a cont...	08/05/2008
7397727	Write burst stop function in low power DDR sDRAM A write burst stop command function is provided for a semiconductor memory device, and in particular for a memory device having a write latency, such as is common in a low power double data rate (DDR) dynamic random access memory (DRAM) device. In the memory device,...	07/08/2008
7391662	Semiconductor memory device with redundancy circuit A semiconductor device has a memory cell, decoders, a redundancy circuit and a mode setting circuit. The memory cell array has word lines including a redundant word line, bit lines and memory cells. A row decoder selects the word lines in response to a row address. ...	06/24/2008
7388797	Semiconductor memory device An apparatus for detecting a defect of a data transfer line in a semiconductor memory device, including a data transfer unit for transferring data between a local I/O line and a global I/O line; a data transfer controller for controlling the data transfer unit by ge...	06/17/2008
7379354	Methods and apparatus to provide voltage control for SRAM write assist circuits Methods and apparatus to control voltage output of a write assist circuit are disclosed. An example method includes regulating pull down voltage from a write assist circuit having a write assist capacitor coupled to a discharge node coupled to a bit line. The write ...	05/27/2008
7379356	Memory, integrated circuit and methods for adjusting a sense amp enable signal used therewith A memory includes at least one memory segment that includes an array of memory cells arranged in a plurality of columns, each of the plurality of columns having a corresponding bitline pair. An address decoder includes a row decoder and a column decoder that address...	05/27/2008
7376010	Nonvolatile semiconductor memory device having protection function for each memory block A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an externa...	05/20/2008
7373575	Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ...	05/13/2008
7372759	Power supply control circuit and controlling method thereof The present invention provides a power supply control circuit and a control method thereof, capable of securing an accurate operation of a GIO in a burst data transmission having a high compression rate. The power supply control circuit of a semiconductor memory dev...	05/13/2008
7366043	Current reduction circuit of semiconductor device A current reduction circuit of a semiconductor device is disclosed which includes an enabling signal generator which outputs a predetermined enabling signal in association with a cell block in which a bridge has been formed between a word line and a bit line, and an...	04/29/2008
7366860	Storage device configured to sequentially input a command A storage device is capable of sequentially inputting a command, which includes address information and attached information, from an information processor through an input/output unit. The storage device includes a storage unit for storing data; an extractor for ex...	04/29/2008
7362641	Method and system for low power refresh of dynamic random access memories A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memo...	04/22/2008
7360049	Non-volatile semiconductor memory device having a password protection function In a nonvolatile semiconductor memory device according to the present invention, a password protection function is enabled or disabled based on a first specified value M and a second state specified value P such that when both of the first specified value M and the ...	04/15/2008
7358758	Apparatus and method for enabling a multi-processor environment on a bus The present invention provides a technique for enabling multiple devices to be interfaced together over a bus that requires dynamic impedance controls. In one embodiment, an apparatus is provided for enabling a multi-device environment on a bus, where the bus requir...	04/15/2008

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

PatentStorm

Quotables

PatentStorm News

Class 365/195 - Inhibit