Class 365/194 - Delay

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter where the particular signal is delayed during
No. of patents: 2100
Last issue date: 05/29/2012

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Number	Title	Issue Date
8189424	Semiconductor memory device having plurality of types of memories integrated on one chip A semiconductor memory device configured to perform a clock synchronous burst read operation includes a plurality of buffer memories having different bank structures, and first and second data latch circuits storing read data read from the plurality of buffer memori...	05/29/2012
8189411	Circuit for controlling an enabling time of an internal control signal according to an operating frequency of a memory device and the method thereof Provided is a circuit for controlling a data bus connecting a bitline sense amplifier to a data sense amplifier in accordance with a variation of an operating frequency of a memory device, being comprised of a pulse width adjusting circuit for varying a pulse width ...	05/29/2012
8184492	Tri-state driver circuits having automatic high-impedance enabling Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay r...	05/22/2012
8179733	Semiconductor integrated circuit device A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and s...	05/15/2012
8169842	Skew detector and semiconductor memory device using the same A skew detection circuit includes a data sensing block configured to sense a first data that is transferred earliest and a last data that is transferred latest among a plurality of data which are transferred through different transfer paths, and generate a sensing r...	05/01/2012
8164965	Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low wr...	04/24/2012
8164964	Boosting voltage levels applied to an access control line when accessing storage cells in a memory A semiconductor memory storage device is disclosed, the memory comprises: a plurality of storage cells for storing data; at least two access control lines each for controlling access to a respective at least one of the plurality of storage cells; at least two access...	04/24/2012
8154935	Delaying a signal communicated from a system to at least one of a plurality of memory circuits A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the sy...	04/10/2012
8144530	Semiconductor memory device and method for generating output enable signal A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and ...	03/27/2012
8144533	Compensatory memory system A compensatory memory system is described. This memory system substantially improves performance by adapting an associated delay in a way that optimizes circuit performance. ...	03/27/2012
8144529	System and method for delay locked loop relock mode Embodiments of the present invention describe a memory device comprising a delay line and a feedback circuit coupled to the delay line. The feedback circuit has the capability to adjust a delay interval, which is then locked on the delay line. The feedback circuit i...	03/27/2012
8144531	Latency control circuit, semiconductor memory device including the same, and method for controlling latency A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information r...	03/27/2012
8144532	Semiconductor memory device and method of controlling same A memory cell is provided at an intersection of a word line and a bit line. A sense amplifier circuit senses and amplifies a signal on the bit line. Replica circuits include a replica cell configured to retain certain data fixedly. A signal detection circuit detects...	03/27/2012
8134877	Semiconductor device having delay control circuit A first delay circuit and a second delay circuit having different operation conditions from each other, a detection circuit that detects a difference in propagation speed of a pulse signal, which is simultaneously input to the first and second delay circuits, and a ...	03/13/2012
8134878	Signal calibration for memory interface A method of calibrating memory controller signals within an integrated circuit (IC) can include determining an internal delay of a clock network of the IC and generating a calibrated clock signal by applying a first delay to an uncalibrated clock signal, wherein the...	03/13/2012
8134886	Method and apparatus for reducing oscillation in synchronous circuits Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal oscillation filtering circuits are described. An oscillation filtering circuit includes a first oscillation filt...	03/13/2012
8125842	Tracking circuit for reducing faults in a memory A memory circuit includes a plurality of memory cells and a plurality of bit lines and row lines connected to the memory cells for accessing selected memory cells. The memory circuit includes a programmable voltage source adapted for connection to at least one bit l...	02/28/2012
8120988	Delay locked loop circuit for preventing failure of coarse locking A delay locked loop circuit includes a delay locked loop receiving an external clock, a frequency detector delaying an input frequency signal to generate a plurality of strobe signals and outputting a check signal indicating that the frequency of the input frequency...	02/21/2012
8116155	Apparatus for measuring data setup/hold time An apparatus for measuring data setup/hold time is capable of effectively measuring a setup/hold time of data, and includes a data generating unit for delaying an external clock signal according to counting signals and generating an internal clock signal and data si...	02/14/2012
8111580	Multi-phase duty-cycle corrected clock signal generator and memory having same Memories, multi-phase clock signal generators, and methods for generating multi-phase duty cycle corrected clock signals are disclosed. For example, one such clock signal generator includes a delay-locked loop having a first multi-tap adjustable delay line configure...	02/07/2012
8107302	Semiconductor integrated circuit device for controlling a sense amplifier A semiconductor IC device includes a command decoder that provides internal read and internal write command signals in response to external command signals, and a delay control unit that is connected with the command decoder and provides an internal read command del...	01/31/2012
8094507	Command latency systems and methods Examples of command latency systems and methods are described. In some examples, phase information associated with a received command signal is stored, a received command signal is propagated through a reduced clock flip-flop pipeline and the delayed command signal ...	01/10/2012
8081527	Per-bit de-skew mechanism for a memory interface controller A memory controller may implement variable delay elements, on a per-bit basis, in both the read and write paths. The memory controller may include multiple adjustable delay circuits associated with data lines and a strobe line, each of the adjustable delay circuits ...	12/20/2011
8072838	Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit and methods for setting a voltage controlled delay Memories, clock synchronization circuits, clock synchronization controller circuits, and methods for setting a voltage controlled delay of a clock synchronization circuit and tracking and recording the control voltage are disclosed. For example, a clock synchronizat...	12/06/2011
8064277	Control circuit of read operation for semiconductor memory apparatus A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first delay unit that is configured to generate and output a first delay signal to a first global input/output line dri...	11/22/2011
8059476	Control component for controlling a delay interval within a memory component Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodic...	11/15/2011
8054701	Delay locked loop and semiconductor memory device with the same A semiconductor memory device is capable of controlling a delay locked loop appropriately based on operation modes, particularly in a fast power-down mode to reduce an amount of current maximumly. The semiconductor memory device includes a delay-locked clock signal ...	11/08/2011
8050120	Sensing delay circuit and semiconductor memory device using the same A sensing delay circuit includes a logic element which responds to a test mode signal to transfer a start signal, a delay unit which is configured of a plurality of inverters having MOS transistors with controlled threshold voltage, and receives external voltage as ...	11/01/2011
8050119	Data output timing in response to read command based on whether delay locked loop is enabled/disabled in a semiconductor device A semiconductor memory device can output data according to a predetermined data output timing, in spite of a high frequency of system clock, even when a delay locked loop is disabled. The semiconductor memory device includes a delay locked loop configured to perform...	11/01/2011
8045407	Memory-write timing calibration including generation of multiple delayed timing signals A memory controller with multiple delayed timing signals. Control information is provided by a first output driver circuit to a first signal path. Write data, associated with the control information, is provided by a second output driver circuit to a second signal p...	10/25/2011
8031540	Randomizing current consumption in memory devices In some implementations, a memory device includes a plurality of memory cells, each memory cell storing a plurality of data bits; an input/output interface that is configured to, in response to receiving a read signal and an address value that identifies a specific ...	10/04/2011
7995422	Burst order control circuit and method thereof A burst order control circuit includes a burst signal generating unit configured to receive a seed column address and to generate a first rising burst signal, a second rising burst signal, a first falling burst signal and a second falling burst signal in response to...	08/09/2011
7990785	Delay locked loop circuit of semiconductor device A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference betwe...	08/02/2011
7990784	Clock signal generating circuit and data output apparatus using the same A semiconductor memory device having a clock signal generating circuit which is capable of controlling a data output in compliance with PVT fluctuation by controlling a output timing of rising and falling clock signal based on a fuse cutting is described. The clock ...	08/02/2011
7990801	Internal write/read pulse generating circuit of a semiconductor memory apparatus A control clock generating unit outputs a clock as a control clock when a column address strobe pulse is input and fixes the control clock to a specific level when an all bank precharge signal or a refresh signal is enabled. An internal pulse generating unit outputs...	08/02/2011
7990786	Read-leveling implementations for DDR3 applications on an FPGA Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a de...	08/02/2011
7986574	Data input circuit technical field A data input circuit comprises a sensing control unit which delays an internal write command by a predetermined period and generates a sense amplifier enable signal in response to a first clock signal, and a data sensing unit which senses align data and transfers th...	07/26/2011
7978547	Data I/O control signal generating circuit in a semiconductor memory apparatus A circuit for generating a data I/O control signal used in a semiconductor memory apparatus comprises a delay block for generating a delay signal having a relatively short delay value and a delay signal having a relatively long delay values, and a selection block fo...	07/12/2011
7969802	Apparatus and method of generating output enable signal for semiconductor memory apparatus A timing signal generator generates a timing signal when an external clock is synchronized with a predetermined internal timing. A frequency-divided clock generator divide a frequency of a DLL (Delay Locked Loop) clock so as to generate an even-numbered divided cloc...	06/28/2011
7965580	Method and apparatus for reducing oscillation in synchronous circuits Control signal oscillation filtering circuits, delay-locked loops, clock synchronization methods and devices and systems incorporating control signal oscillation filtering circuits are described. An oscillation filtering circuit includes a first oscillation filter c...	06/21/2011

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Class 365/194 - Delay