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| Number | Title | Issue Date |
| 6987705 | Memory device with improved output operation margin A synchronous memory device which generates a data output enable signal corresponding to a set CAS latency mode including: a control clock generator for generating an A-type first control clock and a B-type first control clock; a first redundancy enable signal gener... | 01/17/2006 |
| 6981126 | Continuous interleave burst access A system is described which uses a burst access memory and a memory controller to anticipate the memory address to be used in future data read operations as requested by a microprocessor. Either the memory controller or the memory device initiates a burst read opera... | 12/27/2005 |
| 6977864 | Synchronous dynamic random access memory device with single data rate/double data rate mode A data output driver of a combination type of a synchronous dynamic random access memory (SDRAM) device operated in both of a single data rate (SDR) mode and a double data rate (DDR) mode, the data output driver includes a first input/output line connected between a... | 12/20/2005 |
| 6977848 | Data output control circuit A data output control circuit for use in a synchronous semiconductor memory device, which has a plurality of CAS latency modes, includes a signal generating unit for generating an internal signal corresponding to an input command; a CAS latency mode control unit for... | 12/20/2005 |
| 6975557 | Phase controlled high speed interfaces A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circu... | 12/13/2005 |
| 6973009 | Semiconductor memory device capable of switching between an asynchronous normal mode and a synchronous mode and method thereof A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured to output a plurality of data in synchronism with the clock signal af... | 12/06/2005 |
| 6970010 | Apparatus and method for power efficient line driver A method is described that involves driving a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The method also includes holding the second logical value on the... | 11/29/2005 |
| 6967895 | Clock generation circuit and semiconductor memory device using the same In an internal clock control circuit (5) that receives a DQSE signal whose timings have been controlled by a CLK signal received by a register (3) and a write CMD received by an enable signal control circuit (4), by a DQSin signal out... | 11/22/2005 |
| 6961269 | Memory device having data paths with multiple speeds A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of the multiple bi-directional data paths is configured to transfer data at another speed. The memory devic... | 11/01/2005 |
| 6956789 | Cycle ready circuit for self-clocking memory device A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memor... | 10/18/2005 |
| 6957399 | Controlling the propagation of a digital signal by means of variable I/O delay compensation using delay-tracking The propagation of a feedback signal, such as a DQS signal generated in response to a read request in a Double Data Rate (DDR) memory system, into a digital host system, such as an ASIC, is controlled by using delay tracking to compensate for variable I/O delay. The... | 10/18/2005 |
| 6956775 | Write pointer error recovery A write pointer (21) from a write pointer circuit (13) may cause a demultiplexer circuit (12) to direct data from a memory cell (11A–11N) to a desired bit location (0–4) in a register 14. A read pointer (20) may c... | 10/18/2005 |
| 6950350 | Configurable pipe delay with window overlap for DDR receive data A system for maximizing set up and hold times for data reads from a DDR memory device. The system adjusts timing of a strobe from a DDR memory device and converts data from the DDR memory device into a single-data-rate data. The timing adjustment is preferably contr... | 09/27/2005 |
| 6944812 | Mode entry circuit and method An apparatus and method for generating an active mode activation signal in response to an input signal having a voltage exceeding the greater of two reference voltages by a voltage margin. ... | 09/13/2005 |
| 6944070 | Integrated circuit devices having high precision digital delay lines therein Integrated circuit delay devices include a digital delay line that is configured to provide a percent-of-clock period delay to a timing signal accepted at an enabled one of a plurality of injection ports thereof. The digital delay line may be responsive to an inject... | 09/13/2005 |
| 6940321 | Circuit for generating a data strobe signal used in a double data rate synchronous semiconductor device Provided is a circuit for generating a data strobe signal used in a double data rate (DDR) synchronous semiconductor device. The circuit comprises a first logic unit capable of generating a pull up control signal responsive to first and second clock signals. A secon... | 09/06/2005 |
| 6941415 | DRAM with hidden refresh A synchronous DRAM is provided having specified time slots (e.g., every multiple of 4 clock pulses of a DRAM input clock) within which read or write commands may be entered on the command/address bus. During operation, the DRAM performs internally generated refresh ... | 09/06/2005 |
| 6940782 | Memory system and control method for the same A memory system and a control method for the same enable stable operation at high frequencies without a radiant noise problem. In the memory system, a plurality of DRAMs is provided on each of a plurality of modules, and each DRAM is connected with a memory controll... | 09/06/2005 |
| 6940763 | Clock synchronous type semiconductor memory device A synchronous type semiconductor memory device includes a memory cell array in which memory cells are arranged in a matrix; a row address decoder which activates one of word lines in said memory cell array based on a row address in response to a word activation sign... | 09/06/2005 |
| 6938141 | Control chip for accelerating memory access and method of operating the same A control chip for accelerating the memory access and a method of operating the same is disclosed. The disclosed control chip receives a first address strobe (ADS) signal, a request signal, and an address bus signal from the CPU. A second ADS signal will be promptly... | 08/30/2005 |
| 6934199 | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low wr... | 08/23/2005 |
| 6930953 | Self-timed strobe generator and method for use with multi-strobe random access memories to increase memory bandwidth A circuit takes a reference strobe signal as a first input, and a strobe ready signal generated from a memory that is strobed by the reference strobe signal as a second input. The circuit generates a self-timed strobe signal along with other control signals that are... | 08/16/2005 |
| 6930932 | Data signal reception latch control using clock aligned relative to strobe signal A strobe signal is requested from a transmitting device, if no strobe signal has been received within a pre-determined elapsed time. A clock signal aligned relative to an edge of a the strobe signal is generated. One or more data signals received from the transmitti... | 08/16/2005 |
| 6928017 | Semiconductor memory device With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, w... | 08/09/2005 |
| 6924685 | Device for controlling a setup/hold time of an input signal The device for controlling a setup/hold time of an input signal can change a setup/hold time of various control signals applied from an input buffer without physically changing the control device. The device for controlling a setup/hold time of an input signal has t... | 08/02/2005 |
| 6922367 | Data strobe synchronization circuit and method for double data rate, multi-bit writes A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates... | 07/26/2005 |
| 6918016 | Method and apparatus for preventing data corruption during a memory access command postamble An apparatus and method which block the strobing of a data FIFO array in a memory controller of a computer system after the data strobe has entered a fluctuating tristate phase, in particular in the setting of a system using double date rate (DDR) DRAM devices. Such... | 07/12/2005 |
| 6914830 | Distributed write data drivers for burst access memories An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitio... | 07/05/2005 |
| 6909664 | Semiconductor memory device with simplified control of column switches A semiconductor memory device includes a bit line to be coupled to a memory cell, a data-bus line, a gate situated between the bit line and the data-bus line to control a coupling between the bit line and the data-bus line, and a signal generating circuit configured... | 06/21/2005 |
| 6909643 | Semiconductor memory device having advanced data strobe circuit A data strobe circuit for prefetching M number of N bit data, N and M being a positive integer, includes a data strobe buffering unit for generating N number of align control signals based on a data strobe signal; a synchronizing block having M number of latch block... | 06/21/2005 |
| 6908821 | Apparatus for adjusting input capacitance of semiconductor device and fabricating method An apparatus for finely adjusting the input capacitance of a semiconductor device and a method of fabricating the apparatus are disclosed. The invention adjusts finely the input capacitance without increasing a layout area of the device by using a capacitor construc... | 06/21/2005 |
| 6906970 | Address counter strobe test mode device A dynamic random access memory (DRAM) features an address counter strobe test mode device including a reference pulse generator, an address counter strobe test mode unit, an internal address counter unit, and an address decoding unit. The reference pulse generator r... | 06/14/2005 |
| 6889334 | Multimode system for calibrating a data strobe delay for a memory read operation A system for coordinating the timing of a data strobe with data supplied by a memory module to the memory controller read data FIFO of a processor-based system, providing multiple calibration modes. A calibration PDL (programmable delay line) is used to reiterativel... | 05/03/2005 |
| 6880094 | Cas latency select utilizing multilevel signaling A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory modules is provided. Because different memory modules may have different CAS latencies, multilevel signaling is used to standardize the CAS latencies through... | 04/12/2005 |
| 6879527 | Semiconductor memory device with structure providing increased operating speed A semiconductor memory device includes a plurality of memory array blocks including predetermined numbers of memory cells, the memory array blocks being arranged in the row direction; a RAS chain being aligned at a side of the plurality of memory array blocks in the... | 04/12/2005 |
| 6859414 | Data input device in semiconductor memory device A data input device in a semiconductor device, includes a data strobe signal input buffer, which driven in response to a selection signal of a data input/output mode, for receiving a data strobe signal; a data input buffer driven in response to the selection signal;... | 02/22/2005 |
| 6859412 | Circuit for controlling driver strengths of data and data strobe in semiconductor device A circuit for controlling driver strengths of a data and a data strobe in a semiconductor device comprising: a control signal generating unit which generates a first control signal in response to a first address code, generates a second control signal in response to... | 02/22/2005 |
| 6856558 | Integrated circuit devices having high precision digital delay lines therein Integrated circuit delay devices include a digital delay line that is configured to provide a percent-of-clock period delay to a timing signal accepted at an enabled one of a plurality of injection ports thereof. The digital delay line may be responsive to an inject... | 02/15/2005 |
| 6853594 | Double data rate (DDR) data strobe receiver A data strobe receiver that includes a first comparator. The first comparator has a first input that is coupled to a first reference voltage. The first comparator has a second input that is coupled to a data strobe. The first comparator also has an output. The data ... | 02/08/2005 |
| 6850444 | Data input device of a DDR SDRAM A data input device of a DDR SDRAM includes at least a clock pulse generator (for outputting a data-in-strobe signal based on internal clock), first and second data buffers (being controlled by the data-in-strobe signal and having output lines corresponding to first... | 02/01/2005 |
