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| Number | Title | Issue Date |
| 4970687 | Semiconductor memory device having a timing generator circuit which provides a write pulse signal which has an optional timing relationship with the chip select signal A bipolar type RAM having latches which accept and hold address signals, input write data and a write enable signal supplied from outside of the corresponding RAM chip, in accordance with strobe signals, and a timing generator circuit which forms the stro... | 11/13/1990 |
| 4941127 | Method for operating semiconductor memory system in the storage and readout of video signal data A method of employing a semiconductor memory system in the storage and readout of video signal data, wherein first and second FIFO memories are utilized in a tandem manner to perform video-related operations in a plurality of functional modes, such as a f... | 07/10/1990 |
| 4933902 | Method of and apparatus for reducing current of semiconductor memory device A clock generator circuit of a dynamic random access memory (RAM) comprises a power-on reset circuit and an NOR gate conneced to a row address strobe (RAS) terminal and the reset circuit. In operation, the power-on reset circuit generates a one-shot pulse... | 06/12/1990 |
| 4924441 | Method and apparatus for refreshing a dynamic memory An improved memory control and refresh apparatus as shown. For memory read operations, the read only memory and the random access memory are controlled by a signal on conductor (41) and a signal on conductor (40), respectively, so that the read only memor... | 05/08/1990 |
| 4910713 | High input impedance, strobed CMOS differential sense amplifier A general purpose sense amplifier, suited for memory and level shifting applications, is provided. The present invention provides a high input impedence for less loading of bit line voltages, wherein operation is relatively insensitive to capacitive misma... | 03/20/1990 |
| 4901282 | Power efficient static-column DRAM In a static column dynamic random access memory device in which memory operations including refresh operation are initiated responsive to a row address strobe signal, and the refresh operation for amplification and rewriting of information of the selected... | 02/13/1990 |
| 4881206 | Memory device The memory device of this invention comprises a plurality of banks to which common address/data lines are connected, bank-selecting means for selectively feeding data read/write control signals to each bank, and a plurality of circuits for simultaneously ... | 11/14/1989 |
| 4876671 | Semiconductor dynamic memory device with metal-level selection of page mode or nibble mode A semiconductor dynamic memory device is disclosed which contains circuitry for implementing both page mode and nibble modes using a conductor level selection. A clock voltage used in column decoding and output is either coupled to or decoupled from the c... | 10/24/1989 |
| 4875192 | Semiconductor memory with an improved nibble mode arrangement A dynamic semiconductor memory includes a shift register which enables a nibble operation to be carried out, and a timing generator. The timing generator detects every transient state of the column address strobe signals to form shift pulses that are to b... | 10/17/1989 |
| 4866675 | Semiconductor memory circuit having a delay circuit A semiconductor memory circuit includes a variable delay circuit for delaying write data supplied from an external circuit such as a CPU by a delay time which is variably determined depending on a potential level of a write enable signal which is supplied... | 09/12/1989 |
| 4835743 | Semiconductor memory device performing multi-bit Serial operation In a semiconductor memory device capable of nibble mode operation, the time period required from the time when CAS signal falls to the time when a data output buffer activating signal rises is made different at the time of a normal mode and at the time of... | 05/30/1989 |
| 4831597 | Dynamic random access semiconductor memory wherein the RAS and CAS strobes respectively select the bit line and word line pairs A dynamic random access semiconductor memory device includes a bit line pair to which at least one memory cell is connected, a bit line sense amplifier connected between the bit line pair and an input/output line pair, and a word line connected to the mem... | 05/16/1989 |
| 4823324 | Page mode operation of main system memory in a medium scale computer A memory device is disclosed which is comprised of a plurality of memory boards each having at least one memory bank associated therewith with each memory bank including a plurality of memory elements addressable by rows and columns. In page-mode operatio... | 04/18/1989 |
| 4811299 | Dynamic RAM device having a separate test mode capability Disclosed is a dynamic RAM device capable of initiating and cancelling the test mode in response to the combinations of the row address and column address strobe signals with the write enable signal, which combinations are left unused in the normal operat... | 03/07/1989 |
| 4809230 | Semiconductor memory device with active pull up A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/... | 02/28/1989 |
| 4807192 | Memory device employing address multiplexing A memory device employing address multiplexing comprises a counter. An external address is initially set in the counter and a counter address value is incremented responsive to toggle of a column address strobe. The counted address value in the counter is... | 02/21/1989 |
| 4797850 | Dynamic random access memory controller with multiple independent control channels In a data processing system, a DRAM controller which is incorporated on a single semiconductor chip employs multiple column address strobe input signals that drive multiple column address strobe output signals respectively. The multiple signal channels fo... | 01/10/1989 |
| 4792929 | Data processing system with extended memory access A data processing system includes a plurality of memory access devices, each having a characteristic operating speed, for writing data into and reading data from a dynamic random access memory (DRAM) as well as a memory controller for accessing a pluralit... | 12/20/1988 |
| 4788667 | Semiconductor memory device having nibble mode function In the semiconductor memory device havig a nibble mode function, memory cell arrays are divided into two groups of first and second cell blocks. Data bus lines are provided separately to each of the first and second cell blocks. Sense amplifiers are provi... | 11/29/1988 |
| 4685089 | High speed, low-power nibble mode circuitry for dynamic memory A semiconductor dynamic memory device has an array of one-transistor cells, with row and column decode to produce a 4-bit wide input or output from the array. Single-bit data-in and data-out terminals for the device are coupled to the 4-bit array input/ou... | 08/04/1987 |
| 4663741 | Strobed access semiconductor memory system An integrated circuit memory system having an array of ECL memory cells, an address circuit, a READ/WRITE circuit and a coupling circuit which increases the operating current of an addressed memory cell during a READ/WRITE operation. The increased operati... | 05/05/1987 |
| 4636986 | Separately addressable memory arrays in a multiple array semiconductor chip A circuit for inhibiting data transfer to addressed memory locations in a plurality of arrays on a semiconductor chip includes an arbitration circuit (68) that distinguishes between separate inhibit signal inputs on dedicated CAS terminals and multiplexed... | 01/13/1987 |
| 4617647 | Memory circuit A memory circuit which can perform a write operation at a high-speed is disclosed. The memory circuit has an input circuit receiving an external read-write signal which has a direct connection to a terminal receiving a chip control signal such as a column... | 10/14/1986 |
| 4602353 | Integrated semiconductor circuit with a dynamic read-write memory Integrated semiconductor circuit with a dynamic read-write memory having a memory matrix composed of identical memory cells addressable via row and column decoders with respect to the individual memory cells, the addressing of the individual matrix rows b... | 07/22/1986 |
| 4596004 | High speed memory with a multiplexed address bus Memory access time, noise and costs are substantially reduced while reliability is increased by replacing fixed delay lines with a dynamic delay. This dynamic delay is placed on the same integrated circuit as the remainder of the memory access circuitry t... | 06/17/1986 |
| 4586167 | Semiconductor memory device Disclosed is a semiconductor memory device which is operable in a selected one of page mode and nibble mode, depending upon the length of time in which an external column address strobe signal stays at a specific level. The semiconductor memory device com... | 04/29/1986 |
| 4575825 | Semiconductor memory device Disclosed is a semiconductor memory device which is one of three types of semiconductor memory devices, one operable only in page mode, one operable only in nibble and one operable selectively in page mode or nibble mode, being obtained from a partially u... | 03/11/1986 |
| 4547867 | Multiple bit dynamic random-access memory A dynamic MOS random-access memory is described which includes a circuit for permitting checking of the on chip refresh counter. The memory also includes a refresh generator, the frequency of which automatically varies to compensate for temperature variat... | 10/15/1985 |
| 4507761 | Functional command for semiconductor memory A method and apparatus is described for initiating a selected functional mode for a semiconductor memory circuit. The method for initiating the selected functional mode comprises applying an active state of at least a first of the operational signals to t... | 03/26/1985 |
| 4485461 | Memory circuit A memory circuit which can perform consecutive write operations at a high speed is disclosed. The memory circuit comprises a plurality of bus lines, a plurality of memory cell groups associated with the respective bus lines, a plurality of latch circuits ... | 11/27/1984 |
| 4437173 | Core memory controlled by auxiliary core A core memory utilizes an auxiliary core that is driven concurrently with selected data cores to increase tolerances by automatically tracking the peaking time and the output magnitude. Wide variations in both the magnitude and duration of core output swi... | 03/13/1984 |
| 4435792 | Raster memory manipulation apparatus An apparatus for manipulating and displaying raster images stored in a memory system under computer control, wherein a function unit combines new display data presented to the apparatus with display data already stored in memory, to form a new display tha... | 03/06/1984 |
| 4404660 | Circuit and method for dynamically adjusting the voltages of data lines in an addressable memory circuit A two-phase memory circuit provides for adjusting the precharge voltage of a data line to substantially equal the threshold voltage of a sense amplifier coupled to the data line during a first phase so that a relatively small voltage change on the data li... | 09/13/1983 |
| 4397001 | Semiconductor memory device A semiconductor memory device of a dynamic type, including a read/write circuit in a column circuit in which a data input pin and a data output pin are common. The read/write circuit comprises a data-output buffer (DOB) connected through a three-state cir... | 08/02/1983 |
| 4293930 | Bubble detection system There is disclosed a double detection arrangement for minimizing soft errors emanating from a bubble memory. Soft errors are errors due to sporadic, periodic, and random noise which gives an erroneous indication of a bubble's presence. The arrangement pro... | 10/06/1981 |
| 4183095 | High density memory device A high density memory system is formed by reducing the number of electrical conductors that are needed to connect individual memory devices into an operable memory system. The reduction is accomplished by serially reading and writing data from and into se... | 01/08/1980 |
| 4177521 | Output timing arrangement for single-wall magnetic domain apparatus An output timing arrangement for single-wall magnetic domain apparatus for ensuring the concurrence of a domain-generated output signal and the output strobe. Voltages generated at the detector array of the apparatus by its in-plane rotating drive field a... | 12/04/1979 |
| 4164031 | Memory system Disclosed is a memory system for storing digital data; the memory system of the type which may be implemented, for instance, in an electronic microprocessor or calculator system. The memory comprises an array of transistor memory cells arranged in columns... | 08/07/1979 |
| 4163290 | Holographic verification system with indexed memory A verification system utilizing a holographic memory defined by a multiplicity of individual holograms on a photographic strip arranged side by side in elongate, parallel, hologram channels of substantially equal length. A holographic index on the strip i... | 07/31/1979 |
| 4133050 | Early noise pulse and long duration, stabilized switching pulse A large bit size core memory which maximizes usable flux includes at least one array of low drive toroidal magnetic memory cores, a sense-inhibit conductor pair passing through the array in a given direction to inductively couple all cores in the array, a... | 01/02/1979 |
