Class 365/193 - Strobe

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter where the particular signal is used for strobing
No. of patents: 723
Last issue date: 05/01/2012

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Number	Title	Issue Date
8169841	Strobe apparatus, systems, and methods A strobe signal is received in a device and execution of an operation in the device is delayed when the strobe signal includes a preamble. Additional apparatus, systems, and methods are disclosed. ...	05/01/2012
8169840	Address latch circuit and semiconductor memory apparatus using the same An address latch circuit of a semiconductor memory apparatus includes a control signal generating section configured to generate a control signal in response to an external command signal and a RAS idle signal, a clock control section configured to output a clock si...	05/01/2012
8164975	Data capture system and method, and memory controllers and devices Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs f...	04/24/2012
8164963	Semiconductor memory device A semiconductor memory device includes: a first strobe signal generation unit configured to generate a first rising strobe signal in response to a rising DLL clock signal; a second strobe signal generation unit configured to generate a second rising strobe signal in...	04/24/2012
8159887	Clock synchronization in a memory system A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according to a local clock signal 71/73. Based on the resu...	04/17/2012
8159888	Recalibration systems and techniques for electronic memory applications A memory circuit includes a delay module receiving a strobe signal and producing a delayed strobe signal therefrom. The memory circuit also includes a calibration module that initiates recalibration of the delay module when the calibration module discerns that the d...	04/17/2012
8154934	Semiconductor memory device and memory system having the same A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output un...	04/10/2012
8149636	Semiconductor memory device with pulse width determination A semiconductor memory device includes a reset signal generating unit configured to generate a reset control signal by delaying a column command signal by an amount of time varying proportional to an operational frequency. A pulse width determination unit is configu...	04/03/2012
8144528	Memory with data control In an embodiment, a memory device comprises memory, a first data link, a first input, a second input, a second data link, a first output and a second output. The first data link is configured to input one or more packets into the memory device. The first input is co...	03/27/2012
8144527	Semiconductor memory device A semiconductor memory device includes: a data multiplexing unit configured to output one of a data training pattern and data transferred through a first global input/output line in response to a training control signal; and a latch unit configured to latch an outpu...	03/27/2012
8134876	Data input/output apparatus and method for semiconductor system A semiconductor memory device includes: a strobe signal reception unit configured to receive a strobe signal and generate a tracking clock signal; a clock reception unit configured to receive a clock signal and generate an internal clock signal; a plurality of data ...	03/13/2012
8125841	Apparatus for generating output data strobe signal An apparatus for generating an output data strobe signal include a timing control unit configured to detect a specific data pattern and to generate a plurality of timing control signals corresponding to the detected data pattern in response to a clock signal; and a ...	02/28/2012
8111565	Memory interface and operation method of it A memory interface includes a first delaying circuit configured to delay write data to be supplied to an input buffer; a second delaying circuit configured to delay read data read out from an output buffer; a data write circuit configured to supply said write data t...	02/07/2012
8098535	Method and apparatus for gate training in memory interfaces An invention is provided for gate training in memory interfaces. The invention includes adding a coarse delay to a gate assert time, where the coarse delay is a predefined period of time and the gate assert time is a time when a data strobe gate signal is asserted. ...	01/17/2012
8094506	Method and apparatus for timing adjustment A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system...	01/10/2012
8089820	Semiconductor integrated circuit and method thereof A semiconductor IC device which includes a common column signal generating block and a column strobe signal generating block. The common signal generating block can provide precolumn strobe signals by using external command signals and a first group of bank addresse...	01/03/2012
8085608	Signal adjusting system and signal adjusting method A signal adjusting system includes: a signal generating apparatus for transmitting a first driving signal and a second driving signal, a plurality of signal transmitting paths coupled to the signal generating apparatus, and a controlling apparatus coupled to the plu...	12/27/2011
8072826	Memory control circuit and memory control method A memory control circuit includes a data sample circuit, a first delay control circuit, a second delay control circuit and a data circuit. The data sample circuit is used for generating a first data strobe signal and a second data strobe signal. The first delay cont...	12/06/2011
8054700	Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device A semiconductor memory device operates in synchronization with a system clock, without using a synchronous circuit such as a DLL or a PLL. The semiconductor memory device includes a synchronous circuit for generating output signals phase aligned with the system cloc...	11/08/2011
8050118	Semiconductor memory device A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signa...	11/01/2011
8031553	Data strobe signal generating device and a semiconductor memory apparatus using the same A data strobe signal generating device includes a preamble controller configured to generate a preamble signal enabled in synchronization with a first clock signal and disabled in synchronization with a second clock signal after an output enable signal is enabled, a...	10/04/2011
8027210	Data input apparatus with improved setup/hold window In the data input apparatus, a data delay unit outputs data input from outside the data input apparatice. The data delay unit varies the degree of delay in response to a test mode signal. A data alignment signal generating unit receives a first signal synchronized w...	09/27/2011
8023342	Preamble detection and postamble closure for a memory interface controller A memory controller, such as a memory controller for reading data received from a DDR SDRAM memory, may detect the beginning and end of a read cycle. The memory controller may include a preamble detection circuit to receive a strobe signal and output a first control...	09/20/2011
8014218	Capacitively isolated mismatch compensated sense amplifier According to an embodiment of the invention, a sense amplifier for, e.g., an array of DRAM data storage cells includes one or more amplifier stages connected together in series. The amplifier stages together form the sense amplifier for the DRAM array. Each amplifie...	09/06/2011
8009491	Memory access strobe configuration system and process A memory access strobe configuration system and process operable to generate a strobe signal having a selected phase. Based on the strobe signal, a write/read cycle using a first logic value at a memory location of a memory device generates a result logic value. The...	08/30/2011
8009490	Memory interface circuit and memory system including the same The memory interface circuit may include a master delay unit and a slave delay unit. The master delay unit generates a control signal for controlling a delay time based on a clock signal. The slave delay unit selects one signal of an inversion signal of the clock si...	08/30/2011
8009492	Circuit for generating data strobe signal and method A circuit for generating a data strobe signal includes: a control signal generation unit configured to generate a strobe control signal defining an activation time period where a first data strobe signal and a second data strobe signal, which is an inverted signal o...	08/30/2011
8004911	Memory system, memory device, and output data strobe signal generating method An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip...	08/23/2011
7990783	Postamble timing for DDR memories Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A logic circuit, which may be referred to as a one-half period circuit, shortens enable pulses at their fron...	08/02/2011
7990782	Data strobe signal noise protection apparatus and semiconductor integrated circuit A data strobe signal noise prevention apparatus and semiconductor integrated circuit includes a transition protection unit configured to protect a transition of a data strobe signal in response to a control signal and a controller configured to determine when a burs...	08/02/2011
7990781	Write strobe generation for a memory interface controller A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data genera...	08/02/2011
7983112	Semiconductor device which transmits or receives a signal to or from an external memory by a DDR system A semiconductor device in the present invention includes a DLL circuit which determines a phase shift amount, an arithmetic circuit which shifts the phase shift amount by a predetermined phase at test mode time, registers which set the phase shift amount, and a tran...	07/19/2011
7983094	PVT compensated auto-calibration scheme for DDR3 Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. ...	07/19/2011
7983100	Method for generating read enable signal and memory system using the method A method for generating a read enable signal which is for controlling reading of a pair of data strobe signals and a data signal in a memory system is provided. The method comprises: detecting whether the pair of data strobe signals are both high or low; and generat...	07/19/2011
7983101	Circuit for generating data strobe signal in DDR memory device and method therefor The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe si...	07/19/2011
7978546	Memory controller, PCB, computer system and memory adjusting method adjusting a memory output signal characteristic A memory controller, a PCB and a computer system employing the memory controller, and a memory adjusting method using the memory controller. The memory controller interfaces data reading from and writing to a memory and includes: a characteristic estimating part est...	07/12/2011
7974143	Memory system, a memory device, a memory controller and method thereof The memory system, memory device, memory controller and method may have a reduced power consumption. The memory system, memory device, memory controller and method may transition a data strobe signal to a valid logic level during a standby state. The valid logic lev...	07/05/2011
7969801	Data input circuit and nonvolatile memory device including the same A data input circuit includes a first data input unit, a second data input unit, and a clock unit. The first data input unit is configured to receive external data at rising edges of a data strobe signal and output the external data as first internal data in respons...	06/28/2011
7961533	Method and apparatus for implementing write levelization in memory subsystems Methods and apparatus for aligning a clock signal and a set of strobe signals are disclosed. In one embodiment, a memory controller includes a clock generator configured to generate the clock signal, and a respective strobe signal generator configured to generate ea...	06/14/2011
7961534	Semiconductor memory device for writing data to multiple cells simultaneously and refresh method thereof A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a s...	06/14/2011

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Class 365/193 - Strobe