Class 365/191 - Signals

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter where particular signals are used for writing,
No. of patents: 695
Last issue date: 05/15/2012

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Number	Title	Issue Date
8179732	Flash memory devices including ready/busy control circuits and methods of testing the same A flash memory device includes a chip disable fuse circuit that has a fuse and that outputs a chip disable signal when the fuse is cut out, and a ready/busy control circuit that forcibly activates a ready/busy signal representing an internal operational state in res...	05/15/2012
8164962	Semiconductor memory apparatus A semiconductor memory apparatus includes an SRAM circuit having first SRAM cells that store data and second SRAM cells that amplify a potential difference of the data and store the potential difference, a word line driver circuit that outputs a first control signal...	04/24/2012
8139429	Output enable signal generating circuit and method of semiconductor memory apparatus An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control signal having enable timing according to a DLL on/off mode, and an output ...	03/20/2012
RE43162	Semiconductor memory module, electronic apparatus and method for operating thereof A semiconductor memory module (1) includes a circuit substrate (2), a first (100), a second (200), a third (300) and a fourth (400) rank of memory chips (3), a first register (10) and a second register (20	02/07/2012
8107306	Storage devices with soft processing A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signa...	01/31/2012
8107305	Integrated circuit memory operation apparatus and methods Some embodiments include apparatus and methods having a memory cell included in a device, a control line configured to receive a control signal to access the memory cell, and a first line configured to transfer information to and from the memory cell. The control si...	01/31/2012
8089824	Memory controller with staggered request signal output A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the fi...	01/03/2012
8085605	Sequence detection for flash memory with inter-cell interference A memory integrated circuit (IC) includes a read module and a sequence detector module. The read module reads S memory cells (cells) located along one of a bit line and a word line and generates S read signals, where S is an integer greater than 1. The sequence dete...	12/27/2011
8081526	Serialized chip enables A method and system for serializing an enable signal designating an electronic device such as a chip to enable or disable in order to reduce the number of pins and physical signal traces required to provide connections for enable signals of multiple electronic devic...	12/20/2011
8072824	Operation guarantee system An operation guarantee system includes a decoder circuit, a comparison circuit, a CPU circuit, a frequency adjustment circuit and a DQ adjustment circuit. The comparison circuit compares a test data signal input from the decoder circuit with an expected value data s...	12/06/2011
8050117	Command generation circuit and semiconductor memory device There is provided a command generation circuit. The command generation circuit includes a first driving unit driving an output node in response to an internal MRS command and a RAS idle signal; a second driving unit driving the output node in response to an off-sign...	11/01/2011
8045405	Memory system, memory device and command protocol A memory system, memory, and memory system command protocol are disclosed. Within the memory system, a memory controller communicates a command to the memory, the command being selected from a set of commands including a write command and a plurality of non-write co...	10/25/2011
8045406	Latency circuit using division method related to CAS latency and semiconductor memory device A latency circuit for use in a semiconductor memory device includes a latency control clock generator generating an m-divided division signal from an external clock and at least one latency control clock from the m-divided division signal, wherein m is a natural num...	10/25/2011
8040739	Configurable write policy in a memory system A configurable memory system may be able to support at least three different write policies, namely, no-read-on-write, read-before-write, and read-after-write. Such a system may include configurable write signal timing, configurable read signal timing, and/or config...	10/18/2011
8036050	Circuit for transmitting and receiving data and control method thereof A data receiving circuit includes a delay unit for outputting a delayed control signal by delaying a control signal based on a CAS latency, an output driver for time-dividing parallel data based on the control signal and the delayed control signal to generate divide...	10/11/2011
8018791	Circuit, system and method for controlling read latency A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase o...	09/13/2011
8014227	Burst length control circuit and semiconductor memory device using the same A burst length control circuit capable of performing read and write operations in high speed according to a burst length and a semiconductor memory device using the same includes a clock signal generating unit for generating first and second internal clock signals f...	09/06/2011
8004907	SRAM with read and write assist A memory includes an SRAM bitcell including a pair of cross-coupled inverters, wherein a first inverter of the pair includes a first device having a body and a second inverter of the pair includes a second device having a body. A first selection circuit has a first ...	08/23/2011
8000157	RAM macro and timing generating circuit thereof A timing generating circuit generates a control clock (1) and a test clock (2) based on an externally input clock CLK, and outputs the generated clocks to a testing circuit. The control clock (1) is a signal the phase of which is delayed by a pr...	08/16/2011
7995404	Semiconductor IC device and data output method of the same A semiconductor IC device includes a core strobe signal generator configured to latch a read command signal according to an internal clock signal to generate a core strobe signal, a core block configured to output data stored in a memory cell in response to the core...	08/09/2011
7983099	Dual function compatible non-volatile memory device A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physi...	07/19/2011
7969800	Semiconductor memory apparatus A semiconductor memory apparatus includes a row path activating unit configured to generate a line connection control signal according to a received address and active command. The semiconductor memory apparatus also includes a cell array circuit unit including an i...	06/28/2011
7965567	Phase adjustment apparatus and method for a memory device signaling system Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across mul...	06/21/2011
7961532	Bimodal memory controller A memory controller has a communication path which is coupled to an external, wired electrical path. The memory controller includes at least two alternative interface circuits to communicate with the external, wired electrical path using signals having one of two di...	06/14/2011
7957209	Method of operating a memory apparatus, memory device and memory apparatus A memory apparatus includes at least two memory devices, each memory device including at least one memory bank. A method of operating the memory apparatus includes receiving a row activation command generated by a memory controller, wherein the row activation comman...	06/07/2011
7948815	Semiconductor memory device and reset control circuit of the same The semiconductor memory device includes a reset control circuit that monitors a reset signal at an enablement time point of the reset signal input and outputs monitoring signals corresponding to a state of the reset signal. The reset control unit also enables and o...	05/24/2011
7948812	Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory...	05/24/2011
7948814	Semiconductor memory device A semiconductor memory device including a clock input for receiving a source clock and supplying a generated clock to a plurality of clock transmission lines; a plurality of clock amplifiers, each amplifying a respective generated clock loaded on one of the pluralit...	05/24/2011
7944772	Semiconductor memory device and method for generating output enable signal A semiconductor memory device includes a DLL for detecting a phase difference between an external clock signal and a feedback clock signal to generate a delay control signal corresponding to the phase difference, and delaying the external clock signal by a delay amo...	05/17/2011
7936620	Receiver of semiconductor memory apparatus A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or...	05/03/2011
7924636	Electronic circuit device To provide an electronic circuit device that can change a characteristic after package sealing and that achieves a reduction in miscellaneous tasks during characteristic setting. The electronic circuit device includes: a burst detecting circuit 7 for d...	04/12/2011
7916558	Semiconductor memory device and method for reading/writing data thereof A semiconductor memory device is capable of writing data in phase with external data to a memory cell regardless of which memory cell the data is written to. The semiconductor memory device includes a scrambler, a write selector and a read selector. The scrambler is...	03/29/2011
7916557	NAND interface A NAND interface having a reduced pin count configuration, in which all command and address functions and operations of the NAND are provided serially on a single serial command and address pin adapted to receive all commands and addresses, and data communication is...	03/29/2011
7911858	Semiconductor device with DDR memory controller In a DDR memory controller, a clock control circuit is configured to output a clock signal selected from among a plurality of clock signals with different frequencies based on a frequency selection signal, to a DDR memory as an operation clock signal. A master DLL c...	03/22/2011
7898880	Dual port memory device, memory device and method of operating the dual port memory device A dual port memory device converts an address and a control signal, which are inputted via a first port and conform to a first type memory interface, into an address and a control signal which conform to a second type memory interface, to access a memory array. The ...	03/01/2011
7885126	Apparatus for controlling activation of semiconductor integrated circuit An apparatus for controlling an activation of semiconductor integrated circuit includes: an active control unit configured to generate active control signal for determining activation of banks; and a plurality of active signal generating units configured to input th...	02/08/2011
7864624	Semiconductor memory device and method for operating the same A semiconductor memory device includes a first buffering unit configured to buffer a first clock for an address signal and a command to be input in synchronization with the first clock, a second buffering unit configured to buffer a second clock for a data signal to...	01/04/2011
7864604	Multiple address outputs for programming the memory register set differently for different DRAM devices A method, device, and system are disclosed. In one embodiment, the method includes programming a first On Die Termination (ODT) value into a first plurality of dynamic random access memory (DRAM) devices. The first plurality of DRAM devices are located on a dual inl...	01/04/2011
7839704	Memory circuit and control method thereof A memory circuit having a global signal driving circuit, which, when a first read signal is inputted from a first bit signal line with a column signal inputted from a column signal line, outputs the first read signal as a global signal from a global signal line, and...	11/23/2010
7826281	Memory read control circuit A DQS detection circuit 13 detects a preamble of a DQS signal outputted from RAM 11. An up/down counter 14 counts up a number of clock signals CLK) in a period when an DQSEIN signal showing a continuation length of the DQS signal is active, coun...	11/02/2010

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Class 365/191 - Signals