Did You Know...
...that when IBM conducted a market study of Chester Carlson's invention in 1959, the company concluded that it would take only 5000 units of his new product to saturate the market? IBM therefore declined to be part of the new product introduction. Too bad for IBM. Carlson's invention was the xerography process, and his new product was the beginning of the Xerox Corporation. It is estimated that every day, worldwide, 3,000,000,000 copies are made!!
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| Number | Title | Issue Date |
| 8050114 | Memory device having a single pass-gate transistor per bitline column multiplexer coupled to latch circuitry and method thereof A memory device, and method of operation of such a device, are provided. The memory device comprises an array of memory cells arranged in a plurality of rows and a plurality of columns, at least one bit line being associated with each column. Column multiplexer circ... | 11/01/2011 |
| 8045404 | Semiconductor memory device capable of preventing damage to a bitline during a data masking operation A semiconductor memory device includes a memory cell array having a plurality of memory cells coupled between a plurality of word lines and a plurality of bit line pairs, a bit line selection circuit configured to transmit data between a selected bit line pair and a... | 10/25/2011 |
| 8009489 | Memory with read cycle write back A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair of coupling transistors ... | 08/30/2011 |
| 7986573 | Programming memory with direct bit line driving to reduce channel-to-floating gate coupling During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. In connection with a programming iteration, unselected bit lines voltages are stepped ... | 07/26/2011 |
| 7876627 | Semiconductor memory device having a sense amplifier circuit with decreased offset A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down ... | 01/25/2011 |
| 7859921 | Apparatus and method for low power sensing in a multi-port SRAM using pre-discharged bit lines A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first volt... | 12/28/2010 |
| 7855926 | Semiconductor memory device having local sense amplifier with on/off control A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense contro... | 12/21/2010 |
| 7724586 | Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability with minimized area usage A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write op... | 05/25/2010 |
| 7630257 | Methods and systems for accessing memory One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line th... | 12/08/2009 |
| 7613054 | SRAM device with enhanced read/write operations An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary... | 11/03/2009 |
| 7602657 | Semiconductor memory device having floating body cell A semiconductor memory device includes a sense amplifier for the FBC, a first node and a second node can be disconnected from each other by a first isolation transistor. A third node and a fourth node can be disconnected from each other by a second isolation transis... | 10/13/2009 |
| 7596040 | Methods and apparatus for improved write characteristics in a low voltage SRAM Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially droppin... | 09/29/2009 |
| 7463537 | Global bit select circuit interface with dual read and write bit line pairs A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit. ... | 12/09/2008 |
| 7436696 | Read-preferred SRAM cell design A read-preferred SRAM cell includes a pull-up MOS device having a first drive current, a pull-down MOS device coupled to the pull-up MOS device, the pull-down MOS device having a second drive current, and a pass-gate MOS device having a third drive current coupled t... | 10/14/2008 |
| 7436720 | Semiconductor memory device A semiconductor memory device includes plates accessed by different row addresses and a sense amplifier column between the adjacent plates. The sense amplifier column is a mixture of configurations, one in which one of the pair of bit lines is twisted, and another i... | 10/14/2008 |
| 7433223 | Memory devices including floating body transistor capacitorless memory cells and related methods In one aspect, a semiconductor memory device is provided which includes complementary first and second bit lines, a unit memory cell including complementary first and second floating body transistor capacitorless memory cells respectively coupled to the complementar... | 10/07/2008 |
| 7433217 | Content addressable memory cell configurable between multiple modes and method therefor A CAM cell (200) can include a compare section (206) and a configuration section (208). In a binary mode of operation, two compare data values can be driven on value lines VL1 to VL4 (216-0 to 216-3) for comparison ag... | 10/07/2008 |
| 7430147 | Precharge apparatus A precharge circuit prevents voltage dropping of a local input/output line in a semiconductor memory apparatus. The precharge circuit includes at least one pair of pull-up and pull-down precharge circuits. When a local input/output line precharge signal is enabled, ... | 09/30/2008 |
| 7414906 | Memory component having a novel arrangement of the bit lines A memory component comprises a plurality of bit lines, on which memory cells are arranged, and a plurality of sense amplifiers, which are arranged in a row, each sense amplifier being connected to two bit lines. A bit line which is connected to a first sense amplifi... | 08/19/2008 |
| 7411844 | Semiconductor memory device having a redundancy information memory directly connected to a redundancy control circuit A semiconductor memory device (M) includes a memory array (MA) having a plurality of memory cells, a redundancy array (RA) having a plurality of memory cells, a non-volatile redundancy information memory (NVR) having a plurality of memory cells for storing redundanc... | 08/12/2008 |
| 7411813 | Semiconductor device In case that data are written in a flip-flop circuit by inverting the voltage to be supplied to a pair of write bit lines, the peak of the current waveform flowing in the pair of write bit lines is to be made gentler, whereby reduced power source noise and low power... | 08/12/2008 |
| 7408813 | Block erase for volatile memory A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a memory device to a fixed logic level. The memory cells of the block of memory cells are selected and refres... | 08/05/2008 |
| 7397722 | Multiple block memory with complementary data path A memory has a first memory block, a second memory block, a data bus, a first sense amplifier, a second sense amplifier, a first circuit, and a second circuit. The first sense amplifier is coupled to the first memory block. The second sense amplifier is coupled to t... | 07/08/2008 |
| 7391643 | Semiconductor memory device and writing method thereof To provide a semiconductor memory device comprising a phase-change memory and having high compatibility with DRAM interface. The memory cell array 18 comprises a memory cell that includes a phase-change element provided at the intersection of a bit line and w... | 06/24/2008 |
| 7388773 | Random access memory with a plurality of symmetrical memory cells The invention proposes a Random Access Memory (1) with a plurality of symmetrical memory cells (2) which are connected in groups to complementary bit lines (blc, blt), and the complementary bit lines (blc, blt) are coupled through a cross coupled devic... | 06/17/2008 |
| 7379341 | Loading data with error detection in a power on sequence of flash memory device A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and loading nonvolatile memory data and nonvolatile memory complementary data to a read data register and a read complementary data register, respectiv... | 05/27/2008 |
| 7368698 | Imaging device with reduced row readout time and method of operating the same An imager in which a column line bias current control signal is pulsed at some time during and/or after the pulsing of the reset control and the transfer control signals to increase a bias current in a pixel column line during reset and transfer operations. The bias... | 05/06/2008 |
| 7366002 | Method and storage device for the permanent storage of data It is proposed that bitline inversion coding data be integrally stored in the structure of a column multiplexer of a storage device. For this purpose, connections to a predefined potential are selectively provided at connection points, which are respectively assigne... | 04/29/2008 |
| 7362641 | Method and system for low power refresh of dynamic random access memories A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memo... | 04/22/2008 |
| 7362624 | Transistor level shifter circuit A transistor level shifter circuit constituted by a plurality of PMOS TFT is included. The transistor level shifter circuit primarily includes a conversion circuit, a first amplifier circuit, and a second amplifier circuit. With the simplified circuit arrangement an... | 04/22/2008 |
| 7359268 | Semiconductor memory device for low voltage A semiconductor memory device includes a read amplifying unit for transferring a data from a local data line pair to a global data line as a read data; a write driver for transferring a write data from the global data line to the local data line pair; and an input/o... | 04/15/2008 |
| 7359267 | Method of transferring data A method of storing data includes transferring first data from a data line to a first sense amplifier, transferring the first data from the first sense amplifier to a first bit line, and transferring second data from the data line to a second sense amplifier. In the... | 04/15/2008 |
| 7360050 | Integrated circuit memory device having delayed write capability An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command s... | 04/15/2008 |
| 7359254 | Controller for controlling a source current to a memory cell, processing system and methods for use therewith A controller for controlling a source current of a memory cell for use in a static random access memory (SRAM) includes a bias generator for supplying a bias current to the memory cell. A read current generator controls the source current to the memory cell to a rea... | 04/15/2008 |
| 7352609 | Voltage controlled static random access memory A static random access memory (SRAM) (200, 400) comprising a plurality of SRAM cells (204), a plurality of wordlines (WL0-WLN) and a voltage regulator (240, 240′, 300, 516) for driving the wordlines with a wordline voltage signal (VWLP)... | 04/01/2008 |
| 7349274 | Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit l... | 03/25/2008 |
| 7345909 | Low-power SRAM memory cell An SRAM memory cell that has a relatively small power consumption when writing a write value of ‘0’ to the memory cell includes cross-coupled first and second inverters, at least one read access transistor for selectively coupling a respective read bit line to a... | 03/18/2008 |
| 7342839 | Memory cell access circuit A circuit for accessing a memory cell includes a local bitline and a local sense amplifier having a plurality of transistors. The local bitline may be connect the memory cell and the sense amplifier. A first global bitline may be connected to a first one of the plur... | 03/11/2008 |
| 7339842 | Timing control for sense amplifiers in a memory circuit An integrated circuit 18 includes a memory 20 having timing circuitry formed of a global controller 26 and a self-timing path for triggering the sense amplifiers 28 to read bit lines 30 within the array of bit cells 24. The ... | 03/04/2008 |
| RE40132 | Large scale integrated circuit with sense amplifier circuits for low voltage operation Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply vo... | 03/04/2008 |
