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"Transmission of documents via telephone wires is possible in principle, but the apparatus required is so expensive that it will never become a practical proposition."
Dennis Gabor, British physicist
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| Number | Title | Issue Date |
| 8189408 | Memory device having shifting capability and method thereof An array of memory bit cells are operable to provide a memory device having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array can thus be used for conventional me... | 05/29/2012 |
| 8116148 | Low power shift register and semiconductor memory device including the same A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift dock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and ... | 02/14/2012 |
| 8050137 | Semiconductor integrated circuit capable of controlling read command The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read comman... | 11/01/2011 |
| 8045403 | Programming method and memory device using the same A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in ... | 10/25/2011 |
| 8045401 | Supporting scan functions within memories A memory is disclosed comprising: a storage array for storing data; and access circuitry for transmitting data to and from the storage array. The access circuitry forms a data path for inputting and outputting data to the storage array. The access circuitry comprise... | 10/25/2011 |
| 8045400 | Circuit and method for controlling read cycle A circuit for controlling the read cycle includes plurality of shift stages configured to sequentially shift read signals; and an activating unit configured to activate a read cycle signal which represents a read cycle, by performing logical operation for output sig... | 10/25/2011 |
| 8023343 | Systems and methods for issuing address and data signals to a memory array Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked loop may be used to compensate for additional delay experienced by the system clock relative to write clock... | 09/20/2011 |
| 8014217 | Serially loading programming information into a PSR CC/CV controller integrated circuit A primary-side regulation (PSR) controller integrated circuit includes a PSR CC/CV controller and a non-volatile shift register. An assembled power supply that includes the integrated circuit is in-circuit tested to determine errors in power supply output voltage an... | 09/06/2011 |
| 7952942 | Variable reference voltage circuit for non-volatile memory A variable reference voltage circuit for performing memory operation on non-volatile memory includes a multi-level voltage source and a selector circuit. The multi-level voltage source generates multiple voltages. The selector circuit includes a selector input and a... | 05/31/2011 |
| 7855924 | Data processing memory circuit having pull-down circuit with on/off configuration A memory circuit includes a memory cell, a pair of conducting lines operable to signal the logic state of the memory cell and read circuitry operable to perform a read operation by detecting a voltage level of at least one of the pair of conducting lines. The memory... | 12/21/2010 |
| 7852687 | Low power shift register and semiconductor memory device including the same A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift clock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and... | 12/14/2010 |
| 7835203 | Programming method and memory device using the same A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in ... | 11/16/2010 |
| 7808844 | Methods and apparatus for improved memory access A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers a... | 10/05/2010 |
| 7804723 | Semiconductor memory device with signal aligning circuit A signal aligning circuit includes a plurality of pads receiving input signals in parallel 1 bit by 1 bit; a first transferring unit for transferring the input signals as first signals in synchronization with a first clock signal of an internal clock, and transferri... | 09/28/2010 |
| 7733713 | Non-volatile semiconductor storage device A memory cell array includes a plurality of non-volatile semiconductor memory elements, each memory element storing data in a non-volatile manner. A shift register stores data read from the semiconductor memory element and sequentially transfers the data outside, th... | 06/08/2010 |
| 7733714 | MIS-transistor-based nonvolatile memory for multilevel data storage A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/dra... | 06/08/2010 |
| 7668024 | Hybrid static and dynamic sensing for memory arrays A hybrid circuit for a memory includes: a skewed static logic gate circuit; a dynamic pre-discharge device coupled with the skewed static logic gate circuit for operating the static logic gate circuit as a dynamic circuit. ... | 02/23/2010 |
| 7623395 | Buffer circuit and buffer control method A buffer circuit includes a storage unit having a first storage capacity that stores data based on a write request inputted from an outside and outputs the data in an order in which the data was written, based on a read request inputted from the outside. And a secon... | 11/24/2009 |
| 7586797 | Data output circuit of synchronous memory device A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving ... | 09/08/2009 |
| 7573758 | Phase-change random access memory (PRAM) performing program loop operation and method of programming the same A PRAM and programming method are disclosed. The PRAM includes a memory cell array including a test cell, a write driver applying a program pulse and providing a program current to the memory cell array, a sense amplification and verification circuit reading data pr... | 08/11/2009 |
| 7567471 | High speed fanned out system architecture and input/output circuits for non-volatile memory In various embodiments, a plurality of non-volatile memory devices, such as NAND flash memory device, may be connected to a host controller device in a fanned out configuration that allows each of the plurality of memory devices to perform read and/or write operatio... | 07/28/2009 |
| 7561481 | Memory controllers and pad sequence control methods thereof Memory controllers and methods of optimizing pad sequences thereof are provided. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. One memory controller is then provided to have a core logic... | 07/14/2009 |
| 7512021 | Register configuration control device, register configuration control method, and program for implementing the method A resister configuration control device which is capable of updating resister configuration values during a non-display period without increasing a circuit scale. A FIFO selector 103 receives register configuration value information comprising a register conf... | 03/31/2009 |
| 7489568 | Delay stage-interweaved analog DLL/PLL A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized de... | 02/10/2009 |
| 7489567 | FIFO memory device with non-volatile storage stage A FIFO memory device (300) comprises a storage device (321) which is a non-volatile FIFO comprising a plurality of non-volatile storage elements or latches. The FIFO memory device (300) also comprises an input stage (315) which is a volat... | 02/10/2009 |
| 7477553 | Control device for controlling a buffer memory A control device is provided for controlling a buffer memory that can store n data words and is capable of being used for data transfer between a first system and a second system. The control device includes a write pointer and a read pointer. The control device als... | 01/13/2009 |
| 7441072 | Multilevel storage nonvolatile semiconductor memory device enabling high-speed data reading and high-speed data writing A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2n threshold levels. A write d... | 10/21/2008 |
| 7440349 | Integrated semiconductor memory with determination of a chip temperature An integrated semiconductor memory capable of determining a chip temperature includes first control terminals for driving the integrated semiconductor memory with first control signals for performing a write access and second control terminals provided for performin... | 10/21/2008 |
| 7430142 | Skew adjusting circuit and semiconductor integrated circuit An output signal of a flip flop at an output stage is supplied to delay gates connected in series thereto. A selector selects the output signal of the flip flop at the output stage or an output signal of one of the delay gates and supplies the selected signal to an ... | 09/30/2008 |
| 7428474 | Integrated circuit with self-proofreading function and measuring device using the same An integrated circuit (IC) includes a micro control unit (MCU), a one-time programmable (OTP) memory directly connected with the MCU, an electrical charge pump having an output port and an enable port connected to the MCU, and a switching circuit having a control po... | 09/23/2008 |
| 7428178 | Memory circuit containing a chain of stages A memory circuit is provided that includes at least one chain of at least three stages each having a data input, a data output, and a control signal input. Each of the stages between the first stage and the last stage includes a first NMOS transistor having a gate c... | 09/23/2008 |
| 7428183 | Synchronous semiconductor memory device for reducing power consumption A semiconductor memory device capable of reducing power consumption by employing a DLL drive controller. The semiconductor memory device includes: an idle state detector for detecting an idle state that all banks are precharged; a delay locked loop (DLL) for synchro... | 09/23/2008 |
| 7423927 | Wave pipelined output circuit of synchronous memory device Provided is a wave pipelined output circuit of a synchronous memory device. In the wave pipelined output circuit, paths for transferring data in a high frequency mode of the synchronous memory device are separated from paths for transferring the data in a low freque... | 09/09/2008 |
| 7408815 | SRAM cell controlled by flash memory cell First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupl... | 08/05/2008 |
| 7408808 | User configurable commands for flash memory A memory device includes a plurality of memory dies, each having an assigned address. A register on each die is reset on power-up. Boot data is loaded as part of the initialization routine. If the boot data includes a reconfigured command, that command is loaded int... | 08/05/2008 |
| 7403446 | Single late-write for standard synchronous SRAMs Synchronous SRAM may conform to Std. Sync or early-write at an external interface whilst providing late-write internally. ... | 07/22/2008 |
| 7403438 | Memory array architecture and method for high-speed distribution measurements A method includes an initial process of selecting a memory cell within the memory array and an operating condition under which the memory cell is to be tested. The memory cell is tested under the specified operating condition, and a measured response obtained theref... | 07/22/2008 |
| 7403437 | ROM test method and ROM test circuit The present invention provides a ROM test circuit capable of shortening a test time and a test method therefor. When data written into a plurality of ROMs are tested, data of the ROM(1) and ROM(2) are selected based on the output data of the specific R... | 07/22/2008 |
| 7392417 | Device for exchanging data signals between two clock domains A device for transferring data signals between a first clock domain and a second clock domain comprises a serial memory element and a parallel memory element which are coupled. The serial memory element comprises at least one extra memory position more than the para... | 06/24/2008 |
| 7385860 | Data output circuit of synchronous memory device A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving ... | 06/10/2008 |
