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| Number | Title | Issue Date |
| 7170787 | Nonvolatile memory apparatus Current consumption in a nonvolatile memory apparatus operable on two or more different power voltages is to be substantially reduced in its standby mode. A stepped-down power supply unit provided in a flash memory to generate an internal power voltage, when supplie... | 01/30/2007 |
| 7164303 | Delay circuit, ferroelectric memory device and electronic equipment A delay circuit generates an output signal by delaying an input signal, and includes a ferroelectric capacitor having a first end and a second end, a means for inverting a polarization of the ferroelectric capacitor by producing an electric potential difference betw... | 01/16/2007 |
| 7161859 | Semiconductor integrated circuit Voltage transfer switches and voltage input/output circuits are provided on a complementary bus line pair to be shared among a plurality of columns of a memory cell array. After a complementary bit line pair is precharged to a predetermined voltage, the voltage of u... | 01/09/2007 |
| 7161861 | Sense amplifier bitline boost circuit A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost circuit to shorten the charging time for parasitic circuit capacitance. The bitline boost circuit includes... | 01/09/2007 |
| 7161852 | Semiconductor memory device with stable internal power supply voltage A semiconductor memory device having a register for stably generating an internal power supply voltage, including: a pumping circuit unit for generating the internal power supply voltage and adjusting a voltage level of the internal power supply voltage in response ... | 01/09/2007 |
| 7161851 | Method and apparatus for generating multiple system memory drive strengths A system and method for generating multiple drive strengths for one or more output signals of a memory controller operable to control a memory subsystem. The system includes a state machine operable to generate an n-bit output representative of a drive strength oper... | 01/09/2007 |
| 7158424 | Semiconductor memory device In order to decrease the circuit scale of a power supply circuit and the area occupied by the power supply circuit over a semiconductor substrate, the power supply circuit, which supplies a supply voltage to respective parts of a memory circuit, includes a word driv... | 01/02/2007 |
| 7159092 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digit... | 01/02/2007 |
| 7158400 | Method of operating dynamic random access memory A method of operating a dynamic random access memory (DRAM) using a bit line and a bit line bar is disclosed. The DRAM stores data by using a charge storage device, which is coupled to the bit line via a switch device. A voltage drop occurs when the switch device is... | 01/02/2007 |
| 7158412 | On-chip EE-PROM programming waveform generation Circuit methods, and apparatus that provide waveforms having controlled rise and fall times, as well as accurate peak voltages. One embodiment provides circuitry for generating a clock signal and a current that are adjusted for an on-chip capacitance variation. This... | 01/02/2007 |
| 7158180 | System and method for varying exposure time for different parts of a field of view while acquiring an image A system and method for exposing different parts of a single field of view for various and differing lengths of time while capturing an image is provided. For astrophotography, unwanted light pollution or over-saturation bleeding from nearby or obtrusive stars may b... | 01/02/2007 |
| 7158436 | Semiconductor memory devices Semiconductor memory devices. A semiconductor memory device includes a booster circuit generating a predetermined power voltage exceeding an external power voltage, a global power line supplying the predetermined power voltage, and a plurality of memory blocks. Each... | 01/02/2007 |
| 7155561 | Method and system for using dynamic random access memory as cache memory A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs s... | 12/26/2006 |
| 7155581 | Method and apparatus for an energy efficient operation of multiple processors in a memory A method of operating a digital computer includes the steps of addressing a memory, reading a row of data from the memory, providing the same computational instruction simultaneously to each processor element of a plurality of processor elements, where each of the p... | 12/26/2006 |
| 7154776 | Thin film magnetic memory device writing data with bidirectional current An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write... | 12/26/2006 |
| 7154785 | Charge pump circuitry having adjustable current outputs Methods and apparatus are provided. A memory device includes charge pump circuitry having a plurality of parallel charge pumps for supplying a programming voltage to an array of memory cells of the memory device. Each of the charge pumps is adapted to output a fract... | 12/26/2006 |
| 7154786 | Semiconductor integrated circuit device A nonvolatile memory working on a different operating voltage from a logical functional unit is to be operated at high speed with a single line voltage supplied from outside. A nonvolatile memory is disposed in a semiconductor integrated circuit device. This semicon... | 12/26/2006 |
| 7151712 | Row decoder with low gate induce drain leakage current A row decoder with low gate induce drain leakage current (GIDL) comprising a CMOS circuit is provided. The CMOS circuit comprises a first NMOS transistor and a first PMOS transistor. The row decoder of the present invention further comprises a second PMOS transistor... | 12/19/2006 |
| 7151703 | Semiconductor memory device including global IO line with low-amplitude driving voltage signal applied thereto A semiconductor memory device including a global IO line with a low-amplitude driving voltage signal applied thereto. In the device, a first driver converts a data signal of a first voltage level from a memory cell to a second voltage level in response to a read con... | 12/19/2006 |
| 7151707 | Memory device and method having data path with multiple prefetch I/O configurations A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel t... | 12/19/2006 |
| 7151696 | Integrated circuit memory devices having hierarchical bit line selection circuits therein Integrated circuit memory devices include a first column of memory cells electrically coupled to a first pair of bit lines and a bit line precharge and selection circuit. This bit line precharge and selection circuit includes at least one stacked arrangement of thin... | 12/19/2006 |
| 7149109 | Single transistor vertical memory gain cell A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated... | 12/12/2006 |
| 7149132 | Biasing circuit for use in a non-volatile memory device A biasing circuit for use in a non-volatile memory device is coupled to the row decoder and to the column decoder to supply a first and at least a second biasing voltage for the word and bit lines, and includes a first voltage booster having a first input coupled to... | 12/12/2006 |
| 7145821 | Semiconductor memory device for low power system An apparatus included in a semiconductor memory device for precharging a bit line and a bit line bar and sensing and amplifying a data delivered to one of the bit line and the bit line bar. A precharge block precharges the bit line and the bit line bar at a ground. ... | 12/05/2006 |
| 7145381 | Apparatus for controlling a boosted voltage and method of controlling a boosted voltage The apparatus for controlling a boosted voltage includes a voltage generating circuit and a control circuit. The voltage generating circuit is configured to generate a boosted voltage from an input voltage based on a control current, and the control circuit is confi... | 12/05/2006 |
| 7145814 | RAS time control circuit and method for use in DRAM using external clock There is provided a RAS time control circuit for use in a semiconductor memory device. The RAS time control circuit includes a counter for counting the number of external clocks, a comparator for comparing the counted clock number with a preset comparison reference ... | 12/05/2006 |
| 7145363 | Level shifter In a level shifter for receiving a signal of a first voltage level and outputting a signal of a second voltage level, a pull-down driver pulls down a voltage level at an output terminal of the level shifter to a ground voltage level. A pull-up driver and an auxiliar... | 12/05/2006 |
| 7142022 | Clock enable buffer for entry of self-refresh mode A clock enable buffer for entry of a self-refresh mode. The clock enable buffer includes a current mirror load connected between a voltage source and first and second nodes, wherein the current mirror load has first and second transistors; a third transistor connect... | 11/28/2006 |
| 7142465 | Semiconductor memory A semiconductor memory in which a drop in the potential of a bit line due to coupling capacitance at the time of writing data can be restored in a space-saving way without increasing a load at read time. In response to a selection signal, a selection circuit selects... | 11/28/2006 |
| 7139203 | Voltage regulator and data path for a memory device A method and apparatus provide unbalanced output drive capability, for example, to correct for output skews in subsequent output stages. In one aspect, a pre-driver or the like provides unbalanced output drive capability. The pre-driver is comprised of first and sec... | 11/21/2006 |
| 7139211 | Semiconductor memory device for reducing cell area A semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas; a plurality of Y decoders of which one Y decoder selects ... | 11/21/2006 |
| 7138831 | Level conversion circuit and serial/parallel conversion circuit with level conversion function A MOS capacitor receiving a clock signal complementary to a sampling clock signal is provided at an input of a clocked inverter that is activated after sampling an input signal to perform level conversion. A charge pump operation of the MOS capacitor is performed in... | 11/21/2006 |
| 7136311 | Level shifter, level shift circuit, electro-optical device, and electronic apparatus To provide a level shift circuit which has reduced power consumption. A level shift circuit includes level shifters and a control unit. The control unit generates control signals for controlling operation states of the level shifters, respectively. The control unit ... | 11/14/2006 |
| 7137024 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 11/14/2006 |
| 7133960 | Logical to physical address mapping of chip selects In some embodiments, a system and method for mapping the logical chip selects to a physical chip select. A chip select remapping unit receives logical chip select associated with a dual in-line memory module. The chip select remapping unit converts the logical chip ... | 11/07/2006 |
| 7129925 | Dynamic self-refresh display memory A dynamic memory cell for storing data in a display having at least one MEMS device for each pixel has at least two dynamic memory elements per pixel, including first and second dynamic memory elements, each including at least one capacitor, both of the first and se... | 10/31/2006 |
| 7126871 | Circuits and methods to protect a gate dielectric antifuse According to embodiments of the present invention, an antifuse circuit is operated by coupling an elevated voltage to a first terminal of an antifuse, controlling current in the antifuse with a program driver circuit coupled to a second terminal of the antifuse, and... | 10/24/2006 |
| 7126862 | Decoder for memory device A decoder for a memory device includes driving devices each applying a respective line voltage to a respective line of the memory device when turned on. The decoder also includes a control device coupled to the plurality of driving devices at a common node for gener... | 10/24/2006 |
| 7126859 | Semiconductor integrated circuit that handles the input/output of a signal with an external circuit A semiconductor integrated circuit that handles the input/output of a signal with an external circuit. The circuit includes a transistor transmitting a signal between the external circuit and an internal circuit with a drain/source therebetween at a given gate volta... | 10/24/2006 |
| 7126857 | Storage subsystem with embedded circuit for protecting against anomalies in power signal from host A storage subsystem, such as a flash memory card, includes a voltage detection circuit that monitors the power signal from a host system to detect anomalies. The voltage detection circuit responds to a power signal anomaly by asserting a signal, such as a busy signa... | 10/24/2006 |
