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| Number | Title | Issue Date |
| 4543500 | High performance dynamic sense amplifier voltage boost for row address lines A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling tra... | 09/24/1985 |
| 4533843 | High performance dynamic sense amplifier with voltage boost for row address lines A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling tra... | 08/06/1985 |
| 4518879 | Stable rail sense amplifier in CMOS memories A stable sense rail amplifier for CMOS memories is provided allowing very small voltage swings at or very close to the power supply rail to be transformed into substantially rail-to-rail swings. The input of the amplifier is coupled to the output of memor... | 05/21/1985 |
| 4503522 | Dynamic type semiconductor monolithic memory A dynamic type semiconductor memory using MOS transistors, in which first and second booster circuits utilizing capacitances, respectively, are provided at each of stages preceding and succeeding to a word driver, respectively. Data lines of the memory ar... | 03/05/1985 |
| 4499558 | Five-transistor static memory cell implemental in CMOS/bulk A five-transistor CMOS static random-access memory cell which does not require a voltage on the address line higher than the supply voltage to effect writing, and so may be fabricated employing CMOS technology on a bulk single-crystal semiconductor substr... | 02/12/1985 |
| 4484312 | Dynamic random access memory device A dynamic random access memory device which comprises one-transistor, one-capacitor-type memory cells (C00 ~C127,127) in rows and columns and dummy cells (DC20 '~DC2,127 ', DC20 "~DC2,127 "... | 11/20/1984 |
| 4458348 | Electrically programmable read only memory having reduced leakage current An electrically programmable read only memory includes a plurality of non-volatile memory elements having control gates which are commonly connected to a first word line and drains which are coupled to a write-down circuit for supplying a write-down volta... | 07/03/1984 |
| 4455629 | Complementary metal-insulated semiconductor memory decoder A complementary metal-insulated semiconductor (CMIS) which is useful for a highly integrated large-capacity ROM or RAM. The CMIS memory decoder specifies each set of 2m (m is positive integer) word lines of a memory to be accessed by the CMIS m... | 06/19/1984 |
| 4417326 | Static semiconductor memory device A static semiconductor memory device comprises memory cells arranged in a matrix having columns and rows, and bit selection circuits provided in the respective columns. Each of the bit selection circuits is adapted to receive a column selection signal, ha... | 11/22/1983 |
| 4276617 | Transistor switching circuitry A transistor logic circuit wherein a selector is coupled to a pullup resistor and output sense amplifier through an isolation transistor. The selector includes a plurality of transistors having emitter electrodes coupled to a plurality of input terminals,... | 06/30/1981 |
| 4271487 | Static volatile/non-volatile ram cell A volatile/non-volatile RAM cell employing a bistable multivibrator with non-volatile, alterable-threshold capacitors coupled to the output terminals thereof to provide backup data storage in a power-down situation. In one embodiment, the non-volatile cap... | 06/02/1981 |
| 4216395 | Detector circuitry A low power high sensitivity detector having two pairs of MOS cross coupled transistors, voltage equalization circuitry, and a single input, with no external reference, forms the basic configuration of a detector-level shifter circuit which is compatible ... | 08/05/1980 |
| 4207616 | Logic array having improved speed characteristics An integrated circuit Read-Only Memory (ROM) with improved speed of operation is disclosed as generally representative of similarly improved logic arrays. The ROM includes parallel rows of conductors oriented normal to parallel doped regions which form co... | 06/10/1980 |
| 4195356 | Sense line termination circuit for semiconductor memory systems A sense line termination circuit is provided intercoupled between a sense line of a plurality of static memory cells and a supply bus of high pull-up voltage to provide fast access to the memory cells with limited medium power dissipation. The termination... | 03/25/1980 |
| 4181865 | Sensing circuit for a multi-level signal charge This multi-level signal charge sensing circuit includes a first capacitor for holding inspected charge, a second capacitor for holding a plurality of reference charge levels and a comparator for comparing potentials produced at the first and second capaci... | 01/01/1980 |
| 4174541 | Bipolar monolithic integrated circuit memory with standby power enable A bipolar monolithic integrated circuit memory wherein a standby power enable circuit includes a pair of transistors arranged in an active pullup configuration for electrically coupling or decoupling a memory array addressing section of such memory and a ... | 11/13/1979 |
| 4109163 | High speed, radiation hard complementary MOS capacitive voltage level shift circuit A complementary MOS voltage level shift circuit which can be used as a memory buffer circuit, for example, is disclosed. The circuit utilizes both N-channel depletion mode devices and P-channel enhancement mode MOS devices preferably fabricated on silicon... | 08/22/1978 |
| 4096402 | MOSFET buffer for TTL logic input and method of operation An input buffer for MOSFET integrated circuit for receiving low level voltage signals even below the threshold voltages of the transistors comprising the circuit is described. A reference voltage between two logic levels of the input voltage, such as TTL ... | 06/20/1978 |
| 3986054 | High voltage integrated driver circuit Disclosed is a high voltage driver circuit for writing information into a read mostly memory array, the memory cells of the array being characterized by requiring much higher potential levels for writing information than for reading information.... | 10/12/1976 |
| 3976984 | Level shifting circuit device A level shifting circuit device comprises a first terminal connected to a high voltage power source, a P channel type IG-FET whose source and substrate electrodes are connected to said first terminal, means for applying a first pulse signal to the gate el... | 08/24/1976 |
| 3969706 | Dynamic random access memory misfet integrated circuit A MISFET dynamic random access memory chip having 4,096 single transistor, single capacitor storage cells yet packaged in a standard sixteen pin dual inline package is disclosed. Six bit row address and six bit column address data are sequentially multipl... | 07/13/1976 |
| 3967252 | Sense AMP for random access memory A MOSFET random access memory having a highly sensitive sense amplifier is disclosed. The sense amplifier utilizes a field effect transistor connected in the common gate mode so as to produce a large output swing on a relatively low capacitance output nod... | 06/29/1976 |
| 3942160 | Bit sense line speed-up circuit for MOS RAM A speed-up circuit for a bit sense line of an MOS RAM includes a cross-coupled latch circuit having an output coupled to the bit sense line. When partial discharging of the bit sense line is accomplished through the selected storage cell, the latch circui... | 03/02/1976 |
| 3932848 | Feedback circuit for allowing rapid charging and discharging of a sense node in a static memory A feedback circuit for feeding back a signal to control the charging of a sense node in a static MOS memory. A signal from a sense amplifier is fed back to prevent the node from dropping below a predetermined potential and to prepare the node to be rechar... | 01/13/1976 |
