Did You Know...
...that Thomas Edison's patent application on his phonograph was approved by the Patent Office in just seven weeks? In contrast, it took Gordon Gould, the inventor of the laser, 30 years to obtain his patent -- finally awarded in 1988!
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| Number | Title | Issue Date |
| 7366035 | Ferroelectric memory and method of driving the same A ferroelectric memory includes: a memory cell array in which a plurality of memory cells are disposed, a plurality of wordlines, a plurality of platelines, and a plurality of wordline driver circuits, each of the memory cells including a ferroelectric capacitor. A ... | 04/29/2008 |
| 7366048 | Bulk bias voltage level detector in semiconductor memory device There is provided a bulk bias voltage VBB level detector in a semiconductor memory device capable of improving tWR fail generated at a low temperature by compensating a temperature variance. The VBB level detector includes A bulk bias voltage level detector in a sem... | 04/29/2008 |
| 7365585 | Apparatus and method for charge pump slew rate control An apparatus and method for improving memory cell reliability is disclosed. The slew rate is reduced in an applied voltage signal used to program a memory cell when Fowler-Nordheim (FN) tunneling injection is detected. The applied programming signal is provided by a... | 04/29/2008 |
| 7366032 | Multi-ported register cell with randomly accessible history A multi-ported register cell. The register cell includes a base cell and a plurality of history cells, each of which is coupled to the base cell. Each of the plurality history cells is coupled to write to the base cell through a first port, and each of the plurality... | 04/29/2008 |
| 7362158 | Level shifter and a display device having the same A level shifter and a display device having the same are provided. In a level shifter, a first transistor includes a gate electrode receiving a first driving voltage, and a source electrode receiving an input signal through an input terminal. A second transistor inc... | 04/22/2008 |
| 7362646 | Semiconductor memory device A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the memory cells, a switching element group provided in the cell array are... | 04/22/2008 |
| 7362624 | Transistor level shifter circuit A transistor level shifter circuit constituted by a plurality of PMOS TFT is included. The transistor level shifter circuit primarily includes a conversion circuit, a first amplifier circuit, and a second amplifier circuit. With the simplified circuit arrangement an... | 04/22/2008 |
| 7359271 | Gate induced drain leakage current reduction by voltage regulation of master wordline A semiconductor integrated circuit device and method for reducing gate induced leakage current associated with circuits of the semiconductor electrical device, such as a semiconductor integrated circuit memory device. During a standby mode, a voltage supplied to a p... | 04/15/2008 |
| 7358790 | High performance level shift circuit with low input voltage A level shift circuit adds two NMOS transistors or two PMOS transistors between the NMOS transistors and PMOS transistors at the VP-side and the VN-side and connects the gates of the added transistors to the two output terminals. By this architecture, the level shif... | 04/15/2008 |
| 7359254 | Controller for controlling a source current to a memory cell, processing system and methods for use therewith A controller for controlling a source current of a memory cell for use in a static random access memory (SRAM) includes a bias generator for supplying a bias current to the memory cell. A read current generator controls the source current to the memory cell to a rea... | 04/15/2008 |
| 7359255 | Semiconductor device having auto trimming function for automatically adjusting voltage A reference voltage generation circuit generates a reference voltage. An internal voltage generation circuit generates an internal voltage on the basis of the reference voltage generated by the reference voltage generation circuit. A first trimming circuit trims the... | 04/15/2008 |
| 7355906 | SRAM cell design to improve stability A novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) an... | 04/08/2008 |
| 7355904 | Method and apparatus for drain pump operation A method and apparatus are provided for improved noise reduction from switching on and off drain pumps (202) in a high voltage generator. The drain pumps (202) are divided into groups (204) and activation of the groups (204) of drain pump... | 04/08/2008 |
| 7355896 | System for improving endurance and data retention in memory devices A memory system includes a memory block having at least one memory cell. The current is sensed after the erase operations of the memory cell. A signal is generated in response to the current dropping below a predetermined level after the erase operations of the memo... | 04/08/2008 |
| 7355905 | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and wri... | 04/08/2008 |
| 7352649 | High speed array pipeline architecture A memory device including a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output l... | 04/01/2008 |
| 7352633 | Multibit memory cell Provided are a method, system and device for storing multiple bits into a multibit memory cell. In the illustrated embodiment, each multibit memory cell is a “quadbit” cell capable of storing 4 bits which are read out on four bit lines of the cell in response to... | 04/01/2008 |
| 7352616 | Phase change random access memory, boosting charge pump and method of generating write driving voltage A phase change random access memory on aspect includes a memory cell array block including a plurality of phase change memory cells, a column decoder, a row decoder, a column selector, and a write driver. The memory further includes a write boosting unit having a pl... | 04/01/2008 |
| 7349282 | Power voltage supplier of semiconductor memory device The present invention provides a power voltage supplier for stably supplying a noise-free power voltage without increasing a size of a reservoir capacitor by employing a sharing scheme of the reservoir capacitor. The power voltage supplier of a semiconductor memory ... | 03/25/2008 |
| 7350018 | Method and system for using dynamic random access memory as cache memory A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the ... | 03/25/2008 |
| 7348828 | Voltage supplier of semiconductor memory device The present invention provides voltage supplier for supplying an internal voltage with optimized drivability required for internal operation. The voltage supplier of a semiconductor memory device includes: an internal voltage detection means for detecting a voltage ... | 03/25/2008 |
| 7349268 | Voltage generation circuit and semiconductor memory device including the same A voltage generation circuit and semiconductor memory device including the same are provided. The voltage generation circuit includes: a voltage level detector, which detects a level of a first high voltage to generate a first high voltage level detection signal and... | 03/25/2008 |
| 7349240 | Semiconductor memory device having reduced leakage current A static semiconductor memory device includes a memory cell formed in a memory cell region; and a dummy memory cell formed in a dummy memory cell region. The memory cell includes a power supply wiring and a ground wiring which are provided to extend in a direction o... | 03/25/2008 |
| 7349241 | SRAM circuitry A static ram cell is described. The cell includes a pair of cross-coupled transistors and a pair of diode-connected transistors operated from a wordline that provides power to the cell. The cell has three main operating modes, reading, writing, and data retention. R... | 03/25/2008 |
| 7345932 | Low power dissipation voltage generator A voltage generator circuit is described for providing a regulated voltage, such as a negative word line voltage in a semiconductor memory. The generator uses a source transistor to couple a substrate voltage, Vbb, to an output voltage node. The transistor is select... | 03/18/2008 |
| 7345946 | Dual-voltage wordline drive circuit with two stage discharge A wordline driver circuit can include single stage level shifters to translate a low voltage level (VGND to Vcc) to a high voltage level (Vnwl to Vpp). A wordline driver can further include a two-stage discharge circuit to pull down a wordline from a boosted high vo... | 03/18/2008 |
| 7342832 | Bit line pre-settlement circuit and method for flash memory sensing scheme A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to-voltage converters, each of which generates an output voltage based upon the input current f... | 03/11/2008 |
| 7339847 | BLEQ driving circuit in semiconductor memory device A bit line equalization signal (BLEQ) driving circuit for generating an equalization signal used to perform a precharge operation in a semiconductor memory device includes a second boosted voltage generator for producing a second boosted voltage by pumping a supply ... | 03/04/2008 |
| 7336545 | Semiconductor device having switch circuit to supply voltage A memory cell array has memory cells arranged in a matrix form. The memory cell includes a floating gate and a control gate. Word lines are each coupled to the control gates of the memory cells which are arranged on a corresponding one of the rows in the memory cell... | 02/26/2008 |
| 7336552 | Sense amplifier connecting/disconnecting circuit arrangement and method for operating such a circuit arrangement An apparatus and method for operating a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including a switching device for connecting/disconnecting a sense amplifier to/from a bit line of a first cell fiel... | 02/26/2008 |
| 7336121 | Negative voltage generator for a semiconductor memory device A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line dur... | 02/26/2008 |
| 7333385 | Semiconductor memory device having the operating voltage of the memory cell controlled An SRAM circuit operates at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the produced transistor in the SRAM circuit is detected to compare the operat... | 02/19/2008 |
| 7334137 | Memory interface systems that couple a memory to a memory controller and are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller Memory interface systems include one or more channel lines that couple a memory to a memory controller such that the channel line(s) are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller. Because the mem... | 02/19/2008 |
| 7329968 | Charge-recycling voltage domains for energy-efficient low-voltage operation of digital CMOS circuits An integrated circuit with multiple supply voltage domains includes a first domain and a second domain of electrical components. The first domain receives current from a first voltage rail and discharges electrical current to a second voltage rail. A second domain o... | 02/12/2008 |
| 7327598 | High performance, low leakage SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode An SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode is provided. In one embodiment, the SRAM device includes a hierarchical grouping of memory cells of memory cells and biasing circuitry, coupled to the hierarchical g... | 02/05/2008 |
| 7327623 | Energy adjusted write pulses in phase-change memories A memory cell device that includes a plurality of phase-change memory cells, at least one write pulse generator, and at least one temperature sensor. The plurality of phase-change memory cells are each capable of defining at least two states. The write pulse generat... | 02/05/2008 |
| 7327631 | Semiconductor memory device and method of operating semiconductor memory device A semiconductor memory device may include an oscillator circuit for generating an oscillation signal that is varied based on mode of operation, and a word line enable circuit for generating a word line enable signal in response to the oscillation signal. The device ... | 02/05/2008 |
| 7324390 | Low voltage operation dram control circuits Circuits and methods are described for reducing leakage current and speeding access within dynamic random access memory circuit devices. A number of beneficial aspects are described. A circuit is described for an enhanced sense amplifier utilizing complementary drai... | 01/29/2008 |
| 7323926 | Charge pump circuit A charge pump circuit comprises a first pump stage, including a first sub-pump coupled to a first pre-charge MOSFET transistor, wherein the first sub-pump is used to pump down a gate of the first pre-charge MOSFET transistor to thereby increase the pre-charge effici... | 01/29/2008 |
| 7321504 | Static random access memory cell A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter h... | 01/22/2008 |
