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| Number | Title | Issue Date |
| 7085176 | On-chip power-on voltage initialization It has been discovered that initialization of a memory array can be improved by setting the nodes of the memory array to a predetermined value automatically upon applying power to the integrated circuit. Data input nodes and a memory write enable node are configured... | 08/01/2006 |
| 7085178 | Low-power memory write circuits One embodiment of the present invention provides a system that writes to a cell in a memory using a low-voltage-swing signal across a pair of global bit-lines. During operation, the system receives a low-voltage-swing signal across a pair of global bit-lines, which ... | 08/01/2006 |
| 7085174 | Semiconductor memory device with current driver providing bi-directional current to data write line First and second current drivers are connected to one end of corresponding first and second write bit lines, respectively, and the first and second write bit lines are directly connected, at the other end, to a common line. The first and second current drivers recei... | 08/01/2006 |
| 7085190 | Variable boost voltage row driver circuit and method, and memory device and system including same A row driver circuit receives a supply voltage and operates to develop a boosted voltage having a magnitude that is equal to the sum of an incremental boost voltage and a magnitude of the supply voltage. The magnitude of the incremental boost voltage is a function o... | 08/01/2006 |
| 7085975 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 08/01/2006 |
| 7085175 | Word line driver circuit for a static random access memory and method therefor A static random access memory (14) has a normal mode of operation and a low voltage mode of operation. A memory array (15) includes memory cells (16) coupled to a first power supply node (VDD) for receiving a power supply voltage. A p... | 08/01/2006 |
| 7085184 | Delayed bitline leakage compensation circuit for memory devices A delayed bitline leakage compensation circuit for memory devices is disclosed. The delayed bitline leakage compensation circuit includes a bitline leakage model circuit for modeling discharge of a bitline by leakage current in a read operation. It further has a del... | 08/01/2006 |
| 7081772 | Optimizing logic in non-reprogrammable logic devices A method for reducing the amount of logic needed to perform logic operations in non-reprogrammable logic devices based on preexisting circuit designs is provided. The logic optimization method reduces die size and power consumption while increasing the performance o... | 07/25/2006 |
| 7082062 | Voltage output control apparatus and method When the output of a boosted voltage is started by a boosted voltage generation circuit, the voltage supplied to memory cells and level shift circuits side through a current mirror circuit is detected by a voltage divider circuit. Comparators compare the detected vo... | 07/25/2006 |
| 7082067 | Circuit for verifying the write speed of SRAM cells A circuit for measuring the performance of a memory cell. The circuit includes a ring oscillator, which includes a plurality of memory cells. The performance of the memory cell can be determined from an oscillation frequency of the ring oscillator. The circuit accur... | 07/25/2006 |
| 7079412 | Programmable MOS device formed by stressing polycrystalline silicon A programmable memory circuit and a method for programming the same are disclosed. A polycrystalline silicon resistor pair are used in a programmable memory cell. The pair includes a first polycrystalline silicon resistor stressable by a predetermined current therea... | 07/18/2006 |
| 7078953 | Level down converter A level down converter having a first inverter supplied a first power supply voltage, and outputting signals made by logical inversions of input signals, and a second inverter supplied a second power supply voltage being lower than the first power supply voltage, an... | 07/18/2006 |
| 7080180 | Module for insertion into a device and rear panel for insertion into modules A module for inserting into a device with a rear panel comprising a crossed pair of electric lines with a first line and a second line is provided. The module can be connected to the lines of the crossed pair of electric lines by means of a respective plug-in connec... | 07/18/2006 |
| 7079443 | Semiconductor device A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation... | 07/18/2006 |
| 7075838 | Semiconductor device and test method of testing the same A semiconductor device and a method of testing the semiconductor device are provided. The semiconductor device includes a memory cell array, a sense amplifier, a control circuit, a row decoder, a bitline-pair voltage setting circuit, and a wordline driver. The memor... | 07/11/2006 |
| 7075845 | FeRAM and sense amplifier array having data bus pull-down sensing function and sensing method using the same A nonvolatile ferroelectric memory device features a data bus pull-down sensing function. The nonvolatile ferroelectric memory device having a data bus pull-down sensing function comprises a plurality of cell array blocks, a common data bus unit and a sense amplifie... | 07/11/2006 |
| 7075857 | Distributed write data drivers for burst access memories An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitio... | 07/11/2006 |
| 7075339 | Semiconductor output circuit device Comparison circuits are provided, corresponding to a plurality of pull up transistors, each for comparing a voltage at an output node and each respective reference voltage different in voltage level from other, and for adjusting a drive current of a corresponding ou... | 07/11/2006 |
| 7075825 | Electrically alterable non-volatile memory with n-bits per cell An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell can be performed without actually reading the memory state of the cell during the programming operation. A plurality of th... | 07/11/2006 |
| 7075834 | Semiconductor integrated circuit device A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mo... | 07/11/2006 |
| 7075833 | Circuit for detecting negative word line voltage The present invention discloses a circuit for detecting a negative word line voltage including a detecting unit for detecting a negative word line voltage in a detection node by using a plurality of loads coupled in series between a power supply terminal and a negat... | 07/11/2006 |
| 7072235 | Bias sensing in DRAM sense amplifiers through coupling and decoupling device Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled t... | 07/04/2006 |
| 7072238 | Semiconductor device capable of generating ripple-free voltage internally A semiconductor device that generates a regulated high voltage. The device includes, a high voltage generation circuit for supplying a high voltage to the first power line, a current bypass circuit for supplying current to a second power line from the first power li... | 07/04/2006 |
| 7071758 | Voltage level shifter A voltage level shifter is provided. The shifter includes an AND gate for generating a synchronizing signal according to a periodic signal and a primitive input signal. The synchronizing signal and a first periodic control signal that are in phase with the periodic ... | 07/04/2006 |
| 7072230 | Method and apparatus for standby power reduction in semiconductor devices A word line driver circuit for a semiconductor memory device. One or more transistors in the driver circuit are fabricated such that they are susceptible, under certain conditions, to gate-induced diode leakage (GIDL). One terminal of the transistors are coupled to ... | 07/04/2006 |
| 7068547 | Internal voltage generating circuit in semiconductor memory device An internal voltage generating circuit in a semiconductor memory device includes a comparing unit for comparing a voltage level of an internal voltage with that of a reference voltage, a pull-up driving unit for performing a pull-up operation for an output terminal ... | 06/27/2006 |
| 7068548 | Semiconductor integrated circuit with noise reduction circuit A semiconductor integrated circuit includes a substrate, a digital circuit formed on a triple well formed in the substrate, a first node configured to supply a well potential of the digital circuit, a second node separate from the first node, and a substrate-potenti... | 06/27/2006 |
| 7067888 | Semiconductor device and a method of manufacturing the same Semiconductor regions for the suppression of short channel effects are not provided for a pMIS and an nMIS that constitute an inverter circuit of an input first stage of an I/O buffer circuit, whereas semiconductor regions for the suppression of short channel effect... | 06/27/2006 |
| 7068372 | MEMS interferometer-based reconfigurable optical add-and-drop multiplexor The interferometer comprises a beam splitter, a mirror and a phase modulator. The beam splitter splits a signal into a first portion and a second portion. The mirror reflects the first portion. The first portion includes an optical path length, which is fixed. The p... | 06/27/2006 |
| 7068542 | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controll... | 06/27/2006 |
| 7064589 | Semiconductor device using two types of power supplies supplying different potentials A semiconductor device which is driven by a first potential, a second potential lower than the first potential, and a third potential lower than the second potential includes a first Pch transistor and a first Nch transistor connected in series between the first pot... | 06/20/2006 |
| 7064972 | Ferroelectric memory device and read control method thereof A ferroelectric memory device is disclosed, which includes a memory cell array which is formed of a matrix layout of memory cells each having a transistor with its gate connected to a word line and a ferroelectric capacitor having one end connected to a bit line and... | 06/20/2006 |
| 7061793 | Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices A method for small signal sensing during a read operation of a static random access memory (SRAM) cell includes coupling a pair of complementary sense amplifier data lines to a corresponding pair of complementary bit lines associated with the SRAM cell, and setting ... | 06/13/2006 |
| 7061792 | Low AC power SRAM architecture In a SRAM structure, power consumption is reduced by providing a structure which allows specific memory cells to be selected using word lines and column select lines, and reducing the load on the column address lines by dividing the load into sectors. The dividing i... | 06/13/2006 |
| 7061299 | Bidirectional level shifter A bi-directional level shifter for shifting a digital signal from a low power supply voltage level to a high power supply voltage level and vice versa includes first and second I/O terminals, a first circuit operating at a low power supply voltage, and a second circ... | 06/13/2006 |
| 7057257 | Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the ... | 06/06/2006 |
| 7057945 | Non-volatile memory erase circuitry A non-volatile memory device includes floating gate memory cells, a pulse counter and voltage pump control circuitry. The control circuitry selectively activates pumps in response to a count output of the counter. In one embodiment, the pump output current is increa... | 06/06/2006 |
| 7057446 | Reference voltage generating circuit and internal voltage generating circuit for controlling internal voltage level Provided are a reference voltage generating circuit and an internal voltage generating circuit for controlling an internal voltage level, where the reference voltage generating circuit includes a distributing unit, a clamping control unit, and a control unit; the di... | 06/06/2006 |
| 7057819 | High contrast tilting ribbon blazed grating The light modulator includes elongated elements and a support structure coupled to the elongated elements. Each element includes one or more lengthwise slits within an active optical area, and a light reflective planar surface with the light reflective planar surfac... | 06/06/2006 |
| 7053945 | Image sensor having boosted reset A power supply reset boosting element which boosts a level of the reset voltage to a level higher than the level of the power supply. The boosted voltage is isolated from both the power supply and from undesired switching by special transistors which can withstand t... | 05/30/2006 |
