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| Number | Title | Issue Date |
| 8184489 | Level shifting circuit A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a logical high level having a second voltage level at the output where the s... | 05/22/2012 |
| 8174911 | Multi-power domain design In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of tran... | 05/08/2012 |
| 8174910 | Semiconductor device and system for switching between high-voltage and low-voltage operation circuits A semiconductor device includes a first input circuit to which a first supply voltage is supplied, a second input circuit to which a second supply voltage that is lower than the first supply voltage is supplied, and a control circuit which activates the first input ... | 05/08/2012 |
| 8169837 | Semiconductor memory device and method for generating bit line equalizing signal A bit line equalizing signal generator of a semiconductor memory device uses a supply voltage and a pumping voltage in stages during a period where a bit line equalizing signal is enabled, thereby enhancing an equalizing speed and an active speed while minimizing po... | 05/01/2012 |
| 8149644 | Memory system and method that changes voltage and frequency The memory system includes a semiconductor memory that has an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit coupled to the internal circuit and operates according to a second power supply voltage, a fir... | 04/03/2012 |
| 8149634 | Low power memory architecture A memory architecture and circuits for minimizing current leakage in the memory array. Subdivisions of the memory array each have local power grids that can be selectively connected to power supplies, such that only an accessed subdivision will receive power to exec... | 04/03/2012 |
| 8139426 | Dual power scheme in memory circuit A semiconductor memory device includes address signal level shifters configured to transform a low level address signal into a higher level address signal. A decoder is configured to receive the higher level address signal and, in response, provide word line signals... | 03/20/2012 |
| RE43222 | Semiconductor integrated circuit device A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between firs... | 03/06/2012 |
| 8130566 | Sense amplifier and method of sensing data using the same Some embodiments regard a circuit comprising a pre-charge circuit and a latch circuit. The pre-charge circuit charges a voltage node to a pre-determined voltage level based on which the latch circuit generates a feedback signal to stop the pre-charge circuit from ch... | 03/06/2012 |
| 8120974 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device comprising: a memory cell array in which two bit lines are provided to each one bit of input data, and memory cells each including an anti-fuse element are arranged at an intersection point between one of the two bit lines a... | 02/21/2012 |
| 8116147 | Methods and structures for testing SAS-2 speed options in speed negotiation windows Method and structures provide for testing a SAS link during speed negotiation windows to determine success/failure in using a negotiated speed at one or more configured sets of speed options. For each device linked to a master SAS device, each possible set of speed ... | 02/14/2012 |
| 8098533 | Semiconductor memory device with adjustable selected word line potential under low voltage condition A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and tran... | 01/17/2012 |
| 8098534 | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and writ... | 01/17/2012 |
| 8085604 | Snap-back tolerant integrated circuits A method and a circuit for preventing snap-back current in NMOS transistors of MOS integrated circuits are provided. Example embodiments may include preventing snap-back current in a circuit including a first NMOS transistor having an associated parasitic bipolar tr... | 12/27/2011 |
| 8054697 | Semiconductor storage device including a lever shift unit that shifts level of potential of bit line pair A semiconductor storage device includes a level shift unit that shifts level of potential of bit line pair BL, BLB when a sense amplifier starts to read potential of the bit lines. The level shift unit includes level shifting capacitors and a timing gener... | 11/08/2011 |
| 8054696 | System and method to improve reliability in memory word line A method and apparatus are disclosed for improving reliability in a memory circuit. The method includes coupling a pull-down element to a word line, the pull-down element coupled distal to a word line driver. The method further includes, when the word line exhibits ... | 11/08/2011 |
| 8036048 | Semiconductor integrated circuit having DRAM word line drivers A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied... | 10/11/2011 |
| 8018785 | Semiconductor memory device comprising a plurality of static memory cells A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lower... | 09/13/2011 |
| 7990779 | Method of operating semiconductor devices A method of operating a semiconductor device including a memory cell of a 1-T DRAM is provided in which a gate voltage level in a hold mode is adjusted to adjust a data sensing margin of the semiconductor device. ... | 08/02/2011 |
| 7986569 | Semiconductor device A semiconductor device includes a termination driver for driving a data line with a predetermined termination level by using an external power supply voltage and a drive current controller for controlling a drive current flowing into the data line from the terminati... | 07/26/2011 |
| 7986570 | Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port... | 07/26/2011 |
| 7983098 | Adaptive regulator for idle state in a charge pump circuit of a memory device An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduc... | 07/19/2011 |
| 7965564 | Processor arrays made of standard memory cells Standard memory circuits are used for executing a sum-of-products function between data stored in the memory and data introduced into the memory. The sum-of-products function is executed in a manner substantially similar to a standard memory read operation. The memo... | 06/21/2011 |
| 7952941 | Method and apparatus for reducing leakage in bit lines of a memory device A method and system to allow reduction of leakage in the bit lines of a memory device. In addition, minimal delay to the bit lines is introduced by the method and system. The memory device has a plurality of bit lines and a plurality of nodes to facilitate access of... | 05/31/2011 |
| 7948810 | Positive and negative voltage level shifter circuit A level shifter includes a level shifter module that receives a first input signal having high and low states and at least one voltage supply signal, and that generates a latch control signal based on the high and low states of the first input signal. A latch module... | 05/24/2011 |
| 7940580 | Voltage shifting word-line driver and method therefor A memory device is disclosed that includes a plurality of word-lines, with each word-line connected to at least one bitcell. Each of the plurality of word-lines is connected to a corresponding driver module to drive the word-line in response to a corresponding selec... | 05/10/2011 |
| 7924633 | Implementing boosted wordline voltage in memories A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transi... | 04/12/2011 |
| 7885124 | Semiconductor storage device A precharge circuit steps up a voltage of a bit line connected to a memory cell to a power supply voltage. A plurality of step-down circuits step down the voltage of the bit line to a voltage level lower than the power supply voltage before data is read from the mem... | 02/08/2011 |
| 7885125 | Semiconductor memory device having integrated driving word line intermediate voltages by pull-up circuits A semiconductor memory device comprises a logic circuit supplied with a first supply voltage; a cell array supplied with a second supply voltage higher than the first supply voltage and including plural mutually intersecting word lines and bit lines and plural memor... | 02/08/2011 |
| 7881148 | Semiconductor memory device A semiconductor memory device includes a clock supply portion for providing an external clock to the interior of the memory device, a clock transfer portion for transferring the clock from the clock supply portion to each of elements in the memory device and data ou... | 02/01/2011 |
| 7876625 | Semiconductor memory device comprising a plurality of static memory cells A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lower... | 01/25/2011 |
| 7864603 | Memory elements with leakage compensation Integrated circuits with memory elements are provided. The memory elements may be arranged in an array. Data lines may be used to load data into the memory elements and may be used to read data from the memory elements. The memory elements may be used to store confi... | 01/04/2011 |
| 7859919 | Memory device and method thereof The present application discloses a memory array where each memory bit cell of the array includes a level shifter. In addition, each memory bit cell includes a write port that includes pass gate that can include a p-type field effect transistor and an n-type field e... | 12/28/2010 |
| 7852686 | Circuit and method for a sense amplifier with instantaneous pull up/pull down sensing A circuit and method for a sense amplifier for sensing the charge stored when a select signal couples a memory cell to the sense amplifier. A pull up voltage and a pull down voltage are instantaneously supplied to the sense amplifier to sense the small signal differ... | 12/14/2010 |
| 7848158 | Methods and apparatuses for programming flash memory using modulated pulses Methods and apparatuses for programming non-volatile semiconductor memory devices by using modulated pulses are disclosed. An apparatus may have a pulse generator, to create a sequence of pulses and set a threshold voltage of a non-volatile memory cell, and a pulse ... | 12/07/2010 |
| 7839701 | Low voltage operation DRAM control circuits Circuits and methods are described for reducing leakage current and speeding access within dynamic random access memory circuit devices. A number of beneficial aspects are described. A circuit is described for an enhanced sense amplifier utilizing complementary drai... | 11/23/2010 |
| 7835201 | Level-shifter circuit and memory device comprising said circuit A level-shifter circuit is adapted for shift an input voltage into an output voltage that is variable between a negative voltage value up to a preset positive voltage level. The shifter circuit includes a first circuit adapted to shift the input voltage into the pre... | 11/16/2010 |
| 7821850 | Semiconductor digital circuit, FIFO buffer circuit, and data transferring method A FIFO buffer circuit is provided which, in data transmission between two circuit areas having different combinations of a power supply voltage and an operation clock frequency, can perform voltage level and clock rate conversion at the same place and time. In an in... | 10/26/2010 |
| 7800962 | Bit line control circuit for semiconductor memory device A semiconductor memory device includes a bit line sense amplifier for sensing and amplifying data applied on a bit line; a first driver for driving a pull-up voltage line of the bit line sense amplifier to a voltage applied on a normal driving voltage terminal; an o... | 09/21/2010 |
| 7791961 | Semiconductor device and method for boosting word line A semiconductor device of the present invention includes a booster circuit that boosts a selected word line (WL) to a given voltage higher than a power supply voltage and a charge pump circuit that retains the boosted word line (WL) at the first given voltage. When ... | 09/07/2010 |
