Bizarre Patents
Dining Table Having Integral Dishwasher
A space-saving dishwasher, which may be installed within a counter top or table, having a dish-carrying rack that is vertically shiftable through the open top of the dishwasher for facilitating loading and unloading of the dishes.
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| Number | Title | Issue Date |
| 8189404 | Storage device and method for operating the same A storage device includes a control unit, a first voltage supply unit for supplying a first working voltage to the control unit, N memory units, a second voltage supply unit for supplying a second working voltage to each memory unit, a logic gate, a first voltage de... | 05/29/2012 |
| 8120972 | Semiconductor memory apparatus and test circuit therefor A test circuit for a semiconductor memory apparatus of an open bit-line structure includes a compression part configured to, in response to test data read from a plurality of memory cells included in a test target cell mat and a compression control signal generated ... | 02/21/2012 |
| 8064276 | Circuitry and method for indicating a memory Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory type... | 11/22/2011 |
| 8023341 | Method and apparatus for address allotting and verification in a semiconductor device A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row ad... | 09/20/2011 |
| 8014215 | Cache array power savings through a design structure for valid bit detection A mechanism is provided for gating a read access of any row in a cache access memory that has been invalidated. An address decoder in the cache access memory sends a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory ... | 09/06/2011 |
| 7978541 | High speed interface for multi-level memory A solid state memory system includes a first memory chip that includes a plurality of storage elements, and a controller. Each of the plurality of storage elements have a measurable parameter that varies between a lower limit and an upper limit. The controller recei... | 07/12/2011 |
| 7974138 | Semiconductor memory device A semiconductor memory device includes a selector line selection circuit for selecting, in a read operation, a selector line for connecting a first main bit line connected to the sense amplifier with a sub-bit line to which the memory cell being read is connected, a... | 07/05/2011 |
| 7969794 | One-transistor type DRAM A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a... | 06/28/2011 |
| 7898900 | Latency counter, semiconductor memory device including the same, and data processing system To provide a latency counter capable of increasing the signal quality of outputted internal commands. There is provided a point-shift FIFO circuit controlled by count values of a counter circuit. The point-shift FIFO circuit includes: a first wired-OR circuit that c... | 03/01/2011 |
| 7852685 | Semiconductor memory device A semiconductor memory device comprises a first exclusive-OR circuit which compares mth N-bit first data with (m+1)th N-bit second data, a majority circuit which generates flag data to invert the second data if a comparison result of the first exclusive-OR circuit i... | 12/14/2010 |
| 7821849 | Configurable embedded processor A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support differen... | 10/26/2010 |
| 7813154 | Method and apparatus for address allotting and verification in a semiconductor device A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row ad... | 10/12/2010 |
| 7800959 | Memory having self-timed bit line boost circuit and method therefor A memory has an array of memory cells, column logic, a write driver, a voltage detector, and a bootstrap circuit. The array of memory cells is coupled to pairs of bit lines and word lines. The column logic is coupled to the array and is for coupling a selected pair ... | 09/21/2010 |
| 7787314 | Dynamic real-time delay characterization and configuration In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This al... | 08/31/2010 |
| RE41351 | CAM arrays having CAM cells therein with match line and low match line connections and methods of operating same A CAM array including volatile or non-volatile ternary CAM cells that discharge their associated match line through a special discharge line (e.g., a low match line), instead of through the bit line, is disclosed. Each ternary CAM cell includes a pair of storage ele... | 05/25/2010 |
| 7684257 | Area efficient and fast static random access memory circuit and method Disclosed is an accumulation memory circuit for providing a fast read, modify, and write operation in a single clock cycle time. The memory circuit is configured to read data stored in the memory device at an address. The memory circuit includes a reconfigurable add... | 03/23/2010 |
| 7663938 | Tree-style AND-type match circuit device applied to content addressable memory A tree-style AND-type match circuit device applied to the content addressable memory (CAM) is provided. In this tree-style AND-type match circuit device, a plurality of AND-type match circuit groups branchingly connect with each other by a first AND logic gate. The ... | 02/16/2010 |
| 7639551 | Sense amplifiers operated under hamming distance methodology A semiconductor device includes a first sense amplifier coupled to an input for generating a first output; a second sense amplifier couple to the input for generating a second output; and a third sense amplifier coupled to the input for generating a third output, wh... | 12/29/2009 |
| 7602655 | Embedded system An embedded system for programming a programmable device including a micro controller and an I/O interface. The programmable device includes a pin set for signal delivery. The micro controller device controls the programmable device via the pin set. The I/O interfac... | 10/13/2009 |
| RE40894 | Sample and load scheme for observability internal nodes in a PLD A programmable logic device (PLD) that provides the capability to observe and control the logic state of buried internal nodes is disclosed. The PLD provides shadow storage units for internal nodes such as logic element registers, memory cells, and I/O registers. A ... | 09/01/2009 |
| 7548485 | Semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof A semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof are provided. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to write data to a cell in the memory cell ar... | 06/16/2009 |
| 7505331 | Programmable logic device with differential communications support Programmable logic device integrated circuits with differential communications circuitry are provided in which the differential communications circuitry is used to support programming, testing, and user mode operations. Programming operations may be performed on a p... | 03/17/2009 |
| 7495970 | Flexible memory architectures for programmable logic devices Systems and methods provide non-volatile memory architectures for programmable logic devices. For example, a programmable logic device may include logic blocks, input/output blocks, and configuration memory to store configuration data for configuration of the logic ... | 02/24/2009 |
| 7466603 | Memory accessing circuit system A configurable memory system and method is wherein an integrated circuit coupled to a memory device includes application logic and memory interface logic in communication with the application logic, the memory interface logic configured to access a memory array with... | 12/16/2008 |
| 7443739 | Integrated semiconductor memory devices with generation of voltages An integrated semiconductor memory device includes a clock terminal that applies an external clock signal. Read and write accesses are controlled synchronously with the external clock signal. A frequency detector is connected to the clock terminal to detect the freq... | 10/28/2008 |
| 7443742 | Memory arrangement and method for processing data A memory arrangement for processing data comprises a memory, an interface operatively coupled to the memory, a DLL circuit and at least one register device comprising a data input and a clock input. Read data is applied to the interface in response to a read access ... | 10/28/2008 |
| 7440339 | Stacked columnar 1T-MTj MRAM structure and its method of formation and operation This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packi... | 10/21/2008 |
| 7441072 | Multilevel storage nonvolatile semiconductor memory device enabling high-speed data reading and high-speed data writing A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2n threshold levels. A write d... | 10/21/2008 |
| 7436721 | Supplying voltage to a bit line of a memory device A method supplies voltage to a bit line of a memory device. The method includes precharging, with a precharging device, the bit line to an output potential, deactivating the precharging device during a read action related to the bit line, reading, during the read ac... | 10/14/2008 |
| 7433219 | Method and apparatus for address allotting and verification in a semiconductor device A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row ad... | 10/07/2008 |
| 7433248 | System and method for enhanced mode register definitions Apparatus and methods for increasing a number of selectable options for an operating mode. A number of selectable options for an operating mode is increased by programming a first register with data selecting one option of a set of options for the operating mode. A ... | 10/07/2008 |
| 7420863 | Nonvolatile semiconductor memory device which stores multivalue data A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circui... | 09/02/2008 |
| 7417888 | Method and apparatus for resetable memory and design approach for same A resetable memory is described that includes a memory without reset capability having a data output coupled to a first input of a first multiplexer. A second input of the first multiplexer has a reset value input. A channel select for the first multiplexer is coupl... | 08/26/2008 |
| 7414897 | Internal voltage generator capable of regulating an internal voltage of a semiconductor memory device An internal voltage generator maintains stable level of an internal voltage without increasing physical area. The internal voltage generator includes an active level detector for detecting a level of an internal voltage by comparing the level of the internal voltage... | 08/19/2008 |
| 7414916 | Using dedicated read output path to reduce unregistered read access time for FPGA embedded memory A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read output paths for accessing data at the full data width of the memory arr... | 08/19/2008 |
| 7411840 | Sense mechanism for microprocessor bus inversion A sense mechanism for data bus inversion including a first memory device and an analog adder. The first memory device stores bits of the bus in a previous bus cycle. The analog adder compares the bits of the bus in the previous bus cycle with bits of the bus in a cu... | 08/12/2008 |
| 7411804 | Integrated circuit device and electronic instrument An integrated circuit device, including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposi... | 08/12/2008 |
| 7411841 | Memory having storage means A memory capable of inhibiting a non-selected cell from disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, for applying voltages of ... | 08/12/2008 |
| 7408815 | SRAM cell controlled by flash memory cell First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupl... | 08/05/2008 |
| 7403443 | Layout for distributed sense amplifier driver in memory device A semiconductor memory device is disclosed having a layout including, alternating pluralities of memory cell arrays and word line driving blocks arranged next to alternating pluralities of sense amplifier blocks and conjunction blocks, such that each sense amplifier... | 07/22/2008 |
