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| Number | Title | Issue Date |
| 8189402 | Sensing circuit for memory cell supplied with low power An output current of a memory cell is sensed by a sensing circuit for distinguishing a program state and an erase state of the memory cell. The sensing circuit includes a reference transistor, a P-type MOSFET, and an N-type MOSFET. The P-type MOSFET has a gate conne... | 05/29/2012 |
| 8189403 | High speed linear differential amplifier A high speed linear differential amplifier (HSLDA) having automatic gain adjustment to maximize linearity regardless of manufacturing process, changes in temperature, or swing width change of the input signal. The HSLDA comprises a differential amplifier, and a cont... | 05/29/2012 |
| 8149633 | Semiconductor memory device A semiconductor memory device is provided which includes a voltage detecting unit configured to compare a target voltage level with a fed-back internal voltage to output a detection signal in a normal mode, a driving unit configured to selectively drive an internal ... | 04/03/2012 |
| 8139423 | Write driving device A write driving device includes a buffer unit, a duration signal generation unit, and a data input clock pulse generation unit. The buffer unit is configured to generate an alignment signal in response to a transition timing of a data strobe signal. The duration sig... | 03/20/2012 |
| 8125837 | Semiconductor memory device with read/write margin control using back-gate bias The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the... | 02/28/2012 |
| 8125838 | System in package integrated circuit with self-generating reference voltage This invention provides a system in package integrated circuit with self-generating reference voltage, in which includes a logic circuit chip and a memory chip. The logic circuit chip generates a plurality of output signals, and the memory chip includes a plurality ... | 02/28/2012 |
| 8120971 | Internal source voltage generating circuit of semiconductor memory device An internal source voltage generating circuit includes a comparison voltage generator which receives reference and internal source voltages, outputs to a second node a comparison voltage differentially amplified responsive to a voltage of a first node according to a... | 02/21/2012 |
| 8116145 | Method and apparatus for programming auto shut-off A method and system for enabling auto shut-off of programming of a non-volatile memory cell is disclosed. The system includes a memory array having a plurality of memory cells, each cell storing one bit of data. During the programming process, programming signals ar... | 02/14/2012 |
| 8085603 | Method and apparatus for compression of configuration bitstream of field programmable logic A memory is disclosed that can be utilized with a field programmable gate array. In some embodiments, the memory can include a memory array comprising a plurality of memory banks, each memory bank including at least one memory block, each of the at least one memory ... | 12/27/2011 |
| 8077529 | Circuit and method for outputting data in semiconductor memory apparatus A data output circuit of a semiconductor memory apparatus includes a pre-driver generating pull-up and down signals from driving rising and falling data in active periods of rising and falling clocks, respectively, in accordance with a state of an output enable sign... | 12/13/2011 |
| 8064273 | Memory device and methods thereof A memory device is disclosed that includes multiple bit cells, whereby each bit cell is capable of being programmed to more than two states. A value stored at the memory device is determined by comparing the information stored at three or more of the bit cells. In a... | 11/22/2011 |
| 8059481 | Semiconductor memory device A semiconductor memory device includes a memory cell array provided with a main memory cell array including a plurality of memory cells, and a dummy column including a plurality of dummy memory cells, a dummy readout current control section configured to control a c... | 11/15/2011 |
| 8050111 | Data strobe signal generating circuit capable of easily obtaining valid data window A data strobe signal generating circuit includes a pre-driver control unit for selectively transferring a ground voltage and a supply voltage, as a first control signal and a second control signal, in response to first and second clock pulse signals, wherein the sec... | 11/01/2011 |
| 8031538 | Method and apparatus for data inversion in memory device The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the nu... | 10/04/2011 |
| 8027221 | Memory device A memory device that can include a power-supply voltage detector that detects power-supply voltage values and that outputs a detection result indicating which power-supply voltage value is detected; a data-rate setter that sets data rates corresponding to the detect... | 09/27/2011 |
| 8018786 | Method for reading semiconductor memories and semiconductor memory A phase change memory cells including a memory element or a threshold device is read using a read current which does not threshold either the memory element or the threshold device in the case of both a set and a reset memory element. As a result, higher currents ma... | 09/13/2011 |
| 8014214 | Semiconductor memory device A semiconductor memory device is provided which includes a voltage detecting unit configured to compare a target voltage level with a fed-back internal voltage to output a detection signal in a normal mode, a driving unit configured to selectively drive an internal ... | 09/06/2011 |
| 8004909 | Data bus power-reduced semiconductor storage apparatus In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a semiconductor storage apparatus is reduced, thereby reducing the power consumption. For example, a semiconductor st... | 08/23/2011 |
| 7990777 | Method, apparatus and system for transmitting data in semiconductor device Provided is a method of inverting data that is to be transmitted and transmitting the data in a semiconductor device. The method includes inverting bits of data that is to be transmitted if the number of bit transitions of previously transmitted data and the data th... | 08/02/2011 |
| 7990776 | Semiconductor memory device with optimum refresh cycle according to temperature variation A semiconductor memory device, which performs a refresh operation, includes: a temperature sensing unit for measuring temperature and for generating a temperature controlled voltage and a reference current based on the measured temperature; an analog-digital convers... | 08/02/2011 |
| 7983096 | Semiconductor device including nonvolatile memory A semiconductor device includes a nonvolatile memory configured to store write data in a write-enabled state, a check circuit configured to enable the write data as data for comparison in response to an enabled-status indicating signal indicative of the write-enable... | 07/19/2011 |
| 7978544 | Methods for providing a unified view of a domain model to a user Techniques for providing a unified view of a domain model to a user are described herein. In one embodiment, in response to a first search query received from a client via a first search mechanism (e.g., outside of the relational DB) for a list of persistent objects... | 07/12/2011 |
| 7974137 | Semiconductor memory device A semiconductor memory device comprises a comparing unit that comprises a potential of a memory cell with a reference potential supplied by a reference cell to read data of the memory cell; first and second bit lines connected to inputs of the comparing unit; a firs... | 07/05/2011 |
| 7961530 | Semiconductor device including nonvolatile memory A semiconductor device includes a nonvolatile memory configured to store write data in a write-enabled state, a check circuit configured to enable the write data as data for comparison in response to an enabled-status indicating signal indicative of the write-enable... | 06/14/2011 |
| 7944759 | Semiconductor memory device including floating body transistor A semiconductor memory device includes a memory cell array including a plurality of memory cells having a transistor with a floating body, a source line driver configured to control the source lines to select the memory cells in response to an address signal, a sour... | 05/17/2011 |
| 7936614 | Semiconductor memory device and driving method thereof A semiconductor memory device includes a data input driver and a data output driver for receiving an external power supply voltage, and for inputting and outputting data, respectively; and a voltage detector for detecting the external power supply voltage to generat... | 05/03/2011 |
| 7936613 | Semiconductor memory device A charge driving circuit and a discharge driving circuit occupy a relatively small area and maintain driving force in a semiconductor memory device having a plurality of banks. The semiconductor memory device includes multiple banks, a common discharge level detecto... | 05/03/2011 |
| 7916556 | Semiconductor memory device, sense amplifier circuit and memory cell reading method using a threshold correction circuitry A semiconductor memory device includes: a memory cell; a sense line; and a sense amplifier circuit connected to the memory cell via the sense line. The sense amplifier circuit includes a differential sense amplifier, a pull-up section, a read gate transistor, and a ... | 03/29/2011 |
| 7898878 | Methods and apparatus for strobe signaling and edge detection thereof A data system component having a state machine circuit and receivers that utilize high and low threshold signals permits accurate detection of strobe signal pattern edges such as those for preamble, burst and post-amble conditions in the strobe signal. The state mac... | 03/01/2011 |
| 7885131 | Resistance change semiconductor memory device and method of reading data with a first and second switch circuit A semiconductor memory device of the present invention comprises a memory array and a read circuit that reads data of a selected cell. The memory array includes a plurality of memory cells and a reference cell each having a memory element that stores data based on c... | 02/08/2011 |
| 7881128 | Negative word line voltage generator for semiconductor memory device A negative word line voltage generator for semiconductor memory device includes a comparison unit configured to compare a reference voltage and a feedback voltage and to output a comparison result as an output signal, a pull-down driving unit configured to pull down... | 02/01/2011 |
| 7876626 | Semiconductor memory device and semiconductor memory system A semiconductor memory device comprises a memory cell array including a plurality of memory cells arranged at intersections of word lines and bit lines; a read/write circuit operative to execute data read/write to the memory cell; and an operational circuit operativ... | 01/25/2011 |
| 7859939 | Semiconductor memory device A semiconductor memory device includes a clock input unit configured to receive a first clock and a second clock from the external. The memory device further includes a frequency conversion unit configured to convert a frequency of the second clock so that the frequ... | 12/28/2010 |
| 7839702 | Three-dimensional non-volatile register with an oxygen-ion-based memory element and a vertically-stacked register logic A non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below t... | 11/23/2010 |
| 7835197 | Integrated semiconductor memory with generation of data An integrated semiconductor memory with generation of data comprises a clock connection to apply a clock signal, a memory cell array with memory cells to store data of a first data record and a data generator circuit with a first input connection to apply the data o... | 11/16/2010 |
| 7830726 | Data storage using read-mask-write operation Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second... | 11/09/2010 |
| 7826278 | Semiconductor memory device for generating core voltage Semiconductor memory device includes a detection circuit configured to detect a voltage level of an external power supply voltage and a core voltage generation circuit configured to vary a voltage level of the core voltage according to an output signal of the detect... | 11/02/2010 |
| RE41880 | Semiconductor memory device A semiconductor memory device includes (a) a plurality of reference cells, (b) a plurality of memory cells, data stored in a selected reference cell among the reference cells being compared to data stored in a selected memory cell among the memory cells, (c) an addr... | 10/26/2010 |
| 7813191 | Semiconductor memory device overdriving for predetermined period and bitline sense amplifying method of the same A semiconductor memory device overdriving for a predetermined period when sense amplifying a bitline. An overdriving control unit generates an overdriver enabling signal having an enabling period including a point to enable a bitline sense amplifier and a point to s... | 10/12/2010 |
| 7813216 | Reading of the state of a non-volatile storage element A method for reading of the state of a non-volatile memory element, including conditioning the frequency of a first oscillatory to the state of this element, and comparing the frequency of the first oscillator with the predetermined frequency of a second oscillator,... | 10/12/2010 |
