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| Number | Title | Issue Date |
| 8159884 | Nonvolatile semiconductor memory device According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor, a word line, a row decoder, a sense amplifier which determines the data in the memory cell transistor via the bit line, a first bit line clamp transistor connec... | 04/17/2012 |
| 8134874 | Dynamic leakage control for memory arrays A memory circuit is disclosed that comprises a plurality of memory cells coupled to a virtual voltage rail. The plurality of memory cells may form, for example, a sub-array of an SRAM array. A switching circuit may be coupled between the virtual voltage rail and a v... | 03/13/2012 |
| 8102723 | Memory device bit line sensing system and method that compensates for bit line resistance variations Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory ... | 01/24/2012 |
| 8072788 | Flash memory module An embedded processor system including a flash process semiconductor die and a digital process semiconductor die. The flash process semiconductor die includes i) first cache memory configured to cache information associated with an embedded processor, and ii) a firs... | 12/06/2011 |
| 8064271 | Static random access memory device having bit line voltage control for retain till accessed mode and method of operating the same A static random-access memory (SRAM) and a method of controlling bit line voltage. In one embodiment, the SRAM includes: (1) an array of SRAM cells organized in rows and columns, (2) bit lines associated with the columns, (3) a high voltage power supply configured t... | 11/22/2011 |
| 8064272 | Semiconductor memory device A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lin... | 11/22/2011 |
| 8027206 | Bit line voltage control in spin transfer torque magnetoresistive random access memory A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) and associated read operations are disclosed. A bit cell includes a magnetic tunnel junction (MTJ) and a word line transistor, the bit cell being coupled to a bit line and a source line. A clamp... | 09/27/2011 |
| 8009487 | System and method for mitigating reverse bias leakage The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more... | 08/30/2011 |
| 7924632 | Semiconductor memory device A semiconductor memory device comprising: a memory cell array having a plurality of memory cells that are arranged in a shape of a matrix along a plurality of bit lines arranged in parallel and a plurality of word lines intersecting orthogonally to the bit lines, an... | 04/12/2011 |
| 7911854 | Semiconductor memory device A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lin... | 03/22/2011 |
| 7889574 | Semiconductor memory device employing clamp for preventing latch up A semiconductor memory device employs a clamp for preventing latch up. For the purpose, the semiconductor memory device includes a precharging/equalizing unit for precharging and equalizing a pair of bit lines, and a control signal generating unit for producing a co... | 02/15/2011 |
| 7855922 | Memory device bit line sensing system and method that compensates for bit line resistance variations Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory ... | 12/21/2010 |
| 7787313 | Bitline voltage driver A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage... | 08/31/2010 |
| 7755919 | Flash memory module A device includes a first semiconductor die. Nonvolatile memory stores information associated with a second semiconductor die. Cache memory caches a portion of the information. A cache controller controls the cache memory. A device interface communicates the informa... | 07/13/2010 |
| 7751218 | Self-referenced match-line sense amplifier for content addressable memories A design structure for designing, manufacturing, or testing a content addressable memory (CAM) device. The CAM device includes a plurality of CAM cells, match-lines (MLs), search lines, and ML sense amplifiers. The ML sense amplifiers are capable of self-calibration... | 07/06/2010 |
| 7724585 | Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write op... | 05/25/2010 |
| 7724559 | Self-referenced match-line sense amplifier for content addressable memories A content addressable memory (CAM) device and process for searching a CAM. The CAM device includes a plurality of CAM cells, match-lines (MLs), search lines, and ML sense amplifiers. The ML sense amplifiers are capable of self-calibration to their respective thresho... | 05/25/2010 |
| 7706192 | Voltage generating circuits for semiconductor memory devices and methods for the same In a voltage generating circuit for a semiconductor memory device, each of a plurality of reset signal generators individually generates a reset signal in response to one of a plurality of external source voltages. The plurality of external source voltages have diff... | 04/27/2010 |
| 7701783 | Semiconductor storage device A semiconductor storage device has memory cells provided at intersections of word lines and bit lines, a precharge circuit connected to the bit lines, and a write circuit. The write circuit includes a column selection circuit controlled by a write control signal, a ... | 04/20/2010 |
| 7692975 | System and method for mitigating reverse bias leakage The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more... | 04/06/2010 |
| 7672174 | Equalizing circuit for semiconductor memory device A semiconductor memory device includes an equalizing signal generation circuit comprising a clamping circuit that clamps a voltage level less than the voltage level of a high voltage level by being controlled by the high voltage, and an equalizing signal driver rece... | 03/02/2010 |
| 7636264 | Single-ended sense amplifier for very low voltage applications A sense amplifier has a transimpedance amplifier capable of producing an output voltage level proportionate to a current variation sensed going into a bitline. A transconductance device is configured to produce varying bitline current in response to the transimpedan... | 12/22/2009 |
| 7596035 | Memory device bit line sensing system and method that compensates for bit line resistance variations Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory ... | 09/29/2009 |
| 7580296 | Load management for memory device Methods and apparatus for managing electrical loads of electronic devices are disclosed. According to one embodiment, a current load imposed by an electronic device, such as a memory device (or memory system), can be measured. Then, using the measured current load, ... | 08/25/2009 |
| 7570524 | Circuitry for reading phase change memory cells having a clamping circuit A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to... | 08/04/2009 |
| 7539068 | Memory and multi-state sense amplifier thereof The invention provides a multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. The source follower, coupled between a first node and the output terminal of the memory cell, clamps the voltage drop across the memory cell... | 05/26/2009 |
| 7483284 | Flash memory module A device is fabricated on a flash process semiconductor die. The device includes main memory to store processor information. A cache memory caches a portion of the processor information. A cache controller controls the cache memory. A device interface communicates t... | 01/27/2009 |
| 7443752 | Semiconductor memory device amplifying data A semiconductor memory device includes an I/O line, a first sense amplifier connected to the first I/O line to amplify a signal applied on the first I/O line in response to a first control signal, a second sense amplifier for amplifying an output signal of the first... | 10/28/2008 |
| 7440304 | Multiple string searching using ternary content addressable memory A method and apparatus for multiple string searching using a ternary content addressable memory. The method includes receiving a text string having a plurality of characters and performing an unanchored search of a database of a stored patterns matching one or more ... | 10/21/2008 |
| 7440344 | Level shifter for low voltage operation A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors in the voltage level translator is therefore increased, and control o... | 10/21/2008 |
| 7433218 | Flash memory module A device is fabricated on a flash process semiconductor die. The device includes main memory to store processor information. A cache memory caches a portion of the processor information. A cache controller controls the cache memory. A device interface communicates t... | 10/07/2008 |
| 7426127 | Full-rail, dual-supply global bitline accelerator CAM circuit A content-addressable memory circuit includes a first local bit line coupled to a first memory location, a second local bit line coupled to a second memory location, a global bit line coupled to the first and second local bit lines and a global bit line accelerator ... | 09/16/2008 |
| 7426132 | Static random access memory device having a high-bandwidth and occupying a small area An SRAM device is disclosed, which comprises a plurality of rows of SRAM cells and a line-buffer SRAM cell. Each row of SRAM cells is controlled by a word line. The line-buffer SRAM cell is coupled to the rows of SRAM cells and controlled by a read enable line. The ... | 09/16/2008 |
| 7423914 | Data output device and method of semiconductor device The data output device comprises a first comparator for comparing first output data with arbitrary output data on a bit-by-bit basis and outputting a first pre-flag signal, a second comparator for comparing second output data with the first output data on a bit-by-b... | 09/09/2008 |
| 7414897 | Internal voltage generator capable of regulating an internal voltage of a semiconductor memory device An internal voltage generator maintains stable level of an internal voltage without increasing physical area. The internal voltage generator includes an active level detector for detecting a level of an internal voltage by comparing the level of the internal voltage... | 08/19/2008 |
| 7403407 | Magnitude comparator circuit for content addressable memory with programmable priority selection A magnitude comparator circuit can include a bitwise comparison section that includes two passgates for each bit of two values that are compared to one another. The passgates can be enabled according to corresponding bit values of the two values. ... | 07/22/2008 |
| 7400541 | Circuits and methods for data bus inversion in a semiconductor memory A data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits. The DBI block includes a comparison deciding unit configured to generate, in a first mode, a comparison signal b... | 07/15/2008 |
| 7391658 | Internal voltage generator capable of regulating an internal voltage of a semiconductor memory device An internal voltage generator maintains stable level of an internal voltage without increasing physical area. The internal voltage generator includes an active level detector for detecting a level of an internal voltage by comparing the level of the internal voltage... | 06/24/2008 |
| 7388768 | Semiconductor device Control clocks of different phases are distributed to a memory array divided into multiple banks, and processing of entries and search keys (read and write operations and search operation) is performed at different phases. The memory array divided into banks is furt... | 06/17/2008 |
| 7379351 | Non-volatile semiconductor memory and programming method In one aspect, a programming method is provided for a non-volatile semiconductor memory device which includes a plurality of electrically programmable and erasable memory cells, and transmission transistors for providing predetermined voltages to the memory cells. T... | 05/27/2008 |
