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| Number | Title | Issue Date |
| 8189401 | Semiconductor memory device and control method of the same A semiconductor memory device includes a memory cell array including a plurality of memory cells, a first data latch circuit, a second data latch circuit, an arithmetic circuit, a counter circuit, and a controller. And controller compares the number (N) counted by t... | 05/29/2012 |
| 8174907 | Semiconductor device having data input/output unit connected to bus line To provide a semiconductor device including: first and second bus lines; a first buffer connected between the first and second bus lines; second and third buffers connected to the first bus line; fourth and fifth buffers connected to the second bus line; first to fo... | 05/08/2012 |
| 8174906 | Nonvolatile memory device, program method and precharge voltage boosting method thereof, and memory system including the nonvolatile memory device A method of programming a nonvolatile memory device according to the present invention includes precharging bit lines according to data loaded in page buffers; electrically connecting the precharged bit lines to channels corresponding to the bit lines, respectively,... | 05/08/2012 |
| 8174908 | Method of operating memory device having page buffer A method of verifying data in a memory device having a page buffer for performing a program operation, a verifying operation and a read operation, includes: storing data to be programmed in a multi level cell of a first latching circuit in the page buffer; storing r... | 05/08/2012 |
| 8169836 | Buffer control signal generation circuit and semiconductor device A buffer control signal generation circuit includes a burst start signal generator, a command decoder, a burst controller, and a burst column controller. The burst start signal generator shifts a write pulse into a first period to generate a first burst start signal... | 05/01/2012 |
| 8164960 | Write buffering systems for accessing multiple layers of memory in integrated circuits Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a... | 04/24/2012 |
| 8154949 | Burst termination control circuit and semiconductor memory device using the same cross-references to related application A burst termination control circuit includes: a pull-up unit for pulling up a first node in response to a burst termination signal, a latch unit for latching a signal of the first node, a buffer for generating a first termination control signal for stopping data out... | 04/10/2012 |
| 8154933 | Mode-register reading controller and semiconductor memory device A mode-register reading controller includes a switching signal generator, first and second transmitters, and a control signal generator. The switching signal generator generates a switching signal that is activated when the reset command is input during a mode-regis... | 04/10/2012 |
| 8149632 | Output circuit for a semiconductor memory device and data output method An outputting transistor circuit of a push-pull structure has an outputting PMOS transistor and an outputting NMOS transistor connected in series between a first power supply and a grounded power supply. In a standby state, a voltage level of a gate terminal of the ... | 04/03/2012 |
| 8144523 | Semiconductor storage device A semiconductor storage device in accordance with an exemplary aspect of the present invention includes a plurality of memory cells arranged in a matrix pattern, a plurality of word lines each provided so as to correspond to each line of the memory cells, a pluralit... | 03/27/2012 |
| 8144524 | Semiconductor device and semiconductor package including the same To include a plurality of pad groups each including a first data I/O pad, a first power supply pad, a second data I/O pad, and a second power supply pad arranged in order in an X direction. The first data I/O pad is connected to a first data I/O buffer, and the seco... | 03/27/2012 |
| 8139422 | Buffer circuit of semiconductor memory apparatus A buffer circuit of a semiconductor memory apparatus includes a compensation voltage generation unit configured to generate a compensation voltage in response to a level of a reference voltage; and a buffering unit configured to generate an output signal by bufferin... | 03/20/2012 |
| 8130561 | Self pre-charging and equalizing bit line sense amplifier A bit-line sense amplifier includes a latching unit and a control unit. The latching unit has a plurality of field effect transistors coupled between first and second bit lines. The control unit controls application of a bias voltage to a set of the field effect tra... | 03/06/2012 |
| 8130563 | Computer apparatus and memory error signal detecting system A memory error signal detecting system including a signal extracting circuit, a flip-flop, a latch circuit, and a light sign is provided. The signal extracting circuit receives a memory error signal to output a pulse signal when the memory error signal switches from... | 03/06/2012 |
| 8130564 | Semiconductor memory device capable of read out mode register information through DQ pads A semiconductor memory device is provided that is capable of reading out mode register information stored in a register adapted for LPDDR2 (Low Power DDR2), through DQ pads. The semiconductor memory device includes a mode register control unit configured to receive ... | 03/06/2012 |
| 8130562 | Semiconductor memory device having shift registers A semiconductor memory device includes n stages of memory cell units, sense amplifier units, and shift registers. N units of the shift registers are connected to one another on the left end sides. The signal processing units and the reversed signal processing units ... | 03/06/2012 |
| 8125847 | Semiconductor memory device and access method thereof Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in cor... | 02/28/2012 |
| 8120970 | Buffering systems for accessing multiple layers of memory in integrated circuits Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a... | 02/21/2012 |
| 8111559 | Non-volatile random access memory with a control circuit for preventing an initial resistance failure, a solid state drive, and a computer system including the same The non-volatile random access memory (RAM) includes a non-volatile RAM array, a buffer configured to buffer data to be programmed in the non-volatile RAM array and configured to buffer data read from the non-volatile RAM array, and a control block configured to rea... | 02/07/2012 |
| 8107304 | Distributed write data drivers for burst access memories An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating ... | 01/31/2012 |
| 8102721 | Pseudo dual-port memory A pseudo dual-port memory device is disclosed. One embodiment provides an internal data RAM for a microprocessor, and a method for operating a memory device. In one embodiment, a memory device for a microprocessor or microcontroller comprises: a first part with memo... | 01/24/2012 |
| 8102722 | Data output device for semiconductor memory apparatus A data output device of a semiconductor memory apparatus includes detection means configured to detect a specified operation frequency range; pre-driving means configured to be inputted with signals; driving means configured to receive outputs of the pre-driving mea... | 01/24/2012 |
| 8098531 | Semiconductor memory device In a semiconductor memory device which uses a same pad for an address input and data input/output, and has an input circuit and data output circuit connected to the pad, an output of the data output circuit is turned to a high impedance state in accordance with a ch... | 01/17/2012 |
| 8098532 | Non-volatile semiconductor storage device with address search circuit used when writing A non-volatile semiconductor storage device includes a memory cell array having a plurality of non-volatile memory cells, an address search circuit which searches for write object data and outputs an address where the write object data is present, when writing data ... | 01/17/2012 |
| 8094504 | Buffered DRAM A buffered DRAM that can be utilized in a DIMM or RDIMM package to reduce the load on the data lines connected to the package is presented. A buffered DRAM can include a DRAM memory cell; and a buffer coupled to receive data lines and strobe signals, the buffer furt... | 01/10/2012 |
| 8089818 | Nonvolatile semiconductor memory device A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connect... | 01/03/2012 |
| 8089817 | Precise tRCD measurement in a semiconductor memory device A semiconductor memory device is operable in normal and test operation modes. At the test operation, in response to a first active command, a row address signal that is input from the outside is captured in the row decoder, and in response to a first write/read comm... | 01/03/2012 |
| 8085602 | Page buffer circuit, nonvolatile memory device including the page buffer circuit, and method of operating the nonvolatile memory device A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of lat... | 12/27/2011 |
| 8081522 | Page buffer circuit for electrically rewritable non-volatile semiconductor memory device and control method Within a page buffer 14 which is coupled to a non-volatile memory cell array 10 and temporally stores data as the data with a predetermined page unit is written in and read out to/from the memory cell array 10, at least one latch circuit 14 | 12/20/2011 |
| 8077526 | Low power SSTL memory controller An integrated circuit device having configurable resources is configured as a memory controller that includes a plurality of bi-directional pins, an input buffer circuit that is operable to receive SSTL-compliant input and an output buffer that is operable to genera... | 12/13/2011 |
| 8072822 | Data alignment circuit and method of semiconductor memory apparatus A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe clock signal in response to a strobe delay code and generate a delayed strobe clock signal; a plurality of d... | 12/06/2011 |
| 8068372 | Semiconductor memory device A semiconductor memory device includes: a repair node; a fuse one side of which is coupled to the repair node; a pull-down unit configured to selectively transfer a ground voltage to the repair node; a pull-up unit configured to selectively transfer a driving voltag... | 11/29/2011 |
| 8064270 | Semiconductor integrated circuit device A semiconductor integrated circuit device includes a data circuit and a group of bit line application voltage terminals to which different voltages are applied. The data circuit holds program data to be programed into a memory cell and changes the data held accordin... | 11/22/2011 |
| 8054699 | Semiconductor memory device having a double branching bidirectional buffer A semiconductor memory device includes a memory cell array divided into a plurality of areas, a common data bus connected to an input/output circuit, a plurality of individual data buses connected to different areas of the memory cell array through different paths r... | 11/08/2011 |
| 8050110 | Memory device having latch for charging or discharging data input/output line A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line w... | 11/01/2011 |
| 8050109 | Semiconductor memory with improved memory block switching A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circui... | 11/01/2011 |
| 8045399 | Data output circuit in a semiconductor memory apparatus A data output circuit in a semiconductor memory apparatus includes a pre-driver configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driver configured to pull-up drive a first node in response to the pull-up signal and... | 10/25/2011 |
| 8045397 | Semiconductor memory device having common circuitry for controlling address and data mask information A semiconductor memory device is capable of controlling an address and data mask information through the use of a common part, thereby reducing chip size. The semiconductor memory device for receiving the addresses and data mask information via a common pin includes... | 10/25/2011 |
| 8040740 | Semiconductor device with output buffer control circuit for sequentially selecting latched data A semiconductor device includes a data compression circuit that performs sequential processes based on timings of an external clock signal. The sequential processes include compressing data input in parallel, latching the compressed data, and outputting the latched ... | 10/18/2011 |
| 8040753 | System and method for capturing data signals using a data strobe signal A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the... | 10/18/2011 |
