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| Number | Title | Issue Date |
| 8184487 | Modified read operation for non-volatile memory A method may comprise executing a read operation to access a memory array by performing a preactive command to include a row-address-write operation and a bitline precharge and column selection operation and performing an activate command including a column-address-... | 05/22/2012 |
| 8154932 | Increasing efficiency of memory accesses by selectively introducing a relative delay between the time that write addresses are provided to the memory and the time that write data is provided to the memory Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read... | 04/10/2012 |
| 8130557 | Memory system and method of writing into nonvolatile semiconductor memory A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first t... | 03/06/2012 |
| 8117567 | Structure for implementing memory array device with built in computation capability A design structure embodied in a machine readable medium used in a design process includes computational memory device having an array of memory cells arranged in rows and columns, and a pair of read word lines associated with each row of the array. The array is con... | 02/14/2012 |
| 8102720 | System and method of pulse generation In a particular embodiment, a device includes a reference voltage circuit to generate a controlled voltage. The device includes a frequency circuit configured to generate a frequency output signal having a pre-set frequency and a counter to generate a count signal b... | 01/24/2012 |
| 8081538 | Semiconductor memory device and driving method thereof A semiconductor memory device includes output enable signal generation means configured to be reset in response to an output enable reset signal, count a DLL clock signal and an external clock signal, and generate an output enable signal in correspondence to a read ... | 12/20/2011 |
| 8072821 | Semiconductor memory device that can perform successive accesses To provide an input/output circuit that includes a write path to which write data is supplied and a read path to which read data is supplied and first and second data lines that connect the input/output circuit to a memory cell array. The input/output circuit includ... | 12/06/2011 |
| 8068371 | Methods and systems to improve write response times of memory cells Methods and systems to dynamically control state-retention strengths of a plurality of memory cells during a write operation to a subset of the memory cells. Dynamic control may include weakening state-retention strengths of the plurality of memory cells during a wr... | 11/29/2011 |
| 8064269 | Apparatus and methods having majority bit detection Electronic apparatus and fabrication of the electronic apparatus that includes detection of the majority of values in a plurality of data bits may be used in a variety of applications. Embodiments include application of majority bit detection to process data bits in... | 11/22/2011 |
| 8050108 | Semiconductor memory device and semiconductor memory device operation method Provided is a destructive readout semiconductor memory device capable of avoiding concentration of a writeback current, in which a switch circuit (24) is provided between each bit line (21) and each sense amplifier (26). In writeback, the switch... | 11/01/2011 |
| 8009484 | Read circuit and read method In a read circuit, a write circuit writes a data to be stored and/or a test data to the memory cell. A control circuit controls the write circuit to write the test data to the memory cell in a first phase, and to write the test data which is same as the first phase ... | 08/30/2011 |
| 7978543 | Semiconductor device testable on quality of multiple memory cells in parallel and testing method of the same A semiconductor device includes: first and second input/output terminals; a first input/output line connected to the first input/output terminal; a second input/output line connected to the second input/output terminal; and a first by-path route that connects the fi... | 07/12/2011 |
| 7957203 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of me... | 06/07/2011 |
| 7924630 | Techniques for simultaneously driving a plurality of source lines Techniques for simultaneously driving a plurality of source lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for simultaneously driving a plurality of source lines. The apparatus may include a plurality of s... | 04/12/2011 |
| 7916554 | Multi-bank memory accesses using posted writes Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read... | 03/29/2011 |
| 7894280 | Asymmetrical SRAM cell with separate word lines An integrated circuit includes a memory array having a plurality of SRAM memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells. T... | 02/22/2011 |
| 7855933 | Clock synchronization circuit and operation method thereof A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The d... | 12/21/2010 |
| 7848156 | Early read after write operation memory device, system and method A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write da... | 12/07/2010 |
| 7843741 | Memory devices with selective pre-write verification and methods of operation thereof A number of read cycles applied to a selected memory location of a memory device, such as a variable-resistance memory device, is monitored. Write data to be written to the selected memory location is received. Selective pre-write verifying and writing of the receiv... | 11/30/2010 |
| 7839697 | Semiconductor memory device A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit h... | 11/23/2010 |
| 7796444 | Concurrent programming of non-volatile memory One embodiment of the present invention includes applying a first value to a bit line, boosting word lines associated with the bit line and a common selection line to create a first condition based on the first value, and cutting off a boundary non-volatile storage ... | 09/14/2010 |
| 7787312 | Semiconductor device and controlling method for the same A semiconductor device has a plurality of bit lines BL provided in a memory cell area 101, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion source lines VSL provided along the plurality of word lines WL, a... | 08/31/2010 |
| 7787311 | Memory with programmable address strides for accessing and precharging during the same access cycle Embodiments of the present disclosure provide methods, apparatuses and systems including a storage configured to store and output multiple address strides of varying sizes to enable access and precharge circuitry to access and precharge a first and a second group of... | 08/31/2010 |
| 7733738 | Semiconductor memory device and a data write and read method thereof Provided are a semiconductor memory device and a data write and read method thereof. The semiconductor memory device includes a write data controller, an address controller, and a read data controller. The write data controller writes data received with an address t... | 06/08/2010 |
| 7710790 | Semiconductor memory device and write control method thereof A semiconductor memory device comprise a word line, a bit line intersecting the word line, a memory element arranged at intersections of the word line and the bit line and having different required time for a write operation according to a logical value of write dat... | 05/04/2010 |
| 7701781 | Semiconductor memory device with memory cell including a charge storage layer and a control gate and method of controlling the same A semiconductor memory device is capable of simultaneously carrying out a first operation and a second operation. The semiconductor memory device includes first and second control circuits, a select control circuit, and a select circuit. The first control circuit co... | 04/20/2010 |
| 7692974 | Memory cell, memory device, device and method of accessing a memory cell Implementations are presented herein that relate to a memory cell, a memory device, a device and a method of accessing a memory cell. ... | 04/06/2010 |
| 7679971 | Dual port PLD embedded memory block to support read-before-write in one clock cycle A method for a read-before-write functionality for a memory within a programmable logic device (PLD) is provided. The method begins when a read operation and a write operation are initiated through two different ports of a memory simultaneously to access the same ad... | 03/16/2010 |
| 7679970 | Semiconductor memory device for simultaneously performing read access and write access Disclosed herein is a semiconductor memory device which can simultaneously perform a read access and a write access independently. The semiconductor memory device according to the present invention can access a plurality of data through the global sense amplifying u... | 03/16/2010 |
| 7646648 | Apparatus and method for implementing memory array device with built in computational capability A computational memory device includes an array of memory cells arranged in rows and columns, and a pair of read word lines associated with each row of the array. The array is configured to implement, for a given cycle, either a read operation of data contained in a... | 01/12/2010 |
| 7613049 | Method and system for a serial peripheral interface A method for dual I/O data read in an integrated circuit which includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration r... | 11/03/2009 |
| 7583543 | Semiconductor memory device including write selectors A semiconductor memory device includes: static memory cells arranged in a matrix; a read bit line for transmitting data read from one of the memory cells; a write bit line for transmitting data to be written to one of the memory cells; an input data line for transmi... | 09/01/2009 |
| 7570523 | Method for using two data busses for memory array block selection Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory ... | 08/04/2009 |
| 7525849 | Flash memory with sequential programming A method of programming a group of memory cells in a semiconductor memory device selecting a group of memory cells for programming, and enabling a first subgroup of memory cells from the group of memory cells for programming. After enabling the first subgroup, the p... | 04/28/2009 |
| 7505335 | Nonvolatile semiconductor memory device A page mode multi-level NAND-type memory employs two different verify levels per data state and comprises a first data storage circuit which is connected to a memory cell and which stores externally inputted data of a first logic level or a second logic level, a sec... | 03/17/2009 |
| 7486569 | Nonvolatile semiconductor memory A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is p... | 02/03/2009 |
| 7483313 | Dual ported memory with selective read and write protection A device comprising a first port, a second port, and a non-volatile memory. The first port is coupled to and accessible by a first module, and the second port is coupled to and accessible by a second module. The non-volatile memory of the device comprises a first me... | 01/27/2009 |
| 7466607 | Memory access system and method using de-coupled read and write circuits A de-coupled memory access system including a memory access control circuit is configured to generate first and second independent, de-coupled time references. The memory access control circuit includes a read initiate circuit responsive to the first time reference ... | 12/16/2008 |
| 7463535 | Memory modules and memory systems having the same A memory module includes a port configured to receive write data and command/address signals and multiple memory devices. The multiple memory devices include a first set of the memory devices, each memory device of the first set coupled to the port, and a second set... | 12/09/2008 |
| 7443745 | Byte writeable memory with bit-column voltage selection and column redundancy A method for accessing a memory comprising a first set of bit columns, a second set of bit columns, and a redundant set of bit columns, wherein any one of the redundant set of bit columns can be substituted for one of the first set of bit columns or one of the secon... | 10/28/2008 |
