Class 365/189.02 - Multiplexing

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter which includes the transmission of plural
No. of patents: 1061
Last issue date: 05/29/2012

«First «Previous 4 5 6 7 8 9 10 11 12 13 14 Next»Last»

Number	Title	Issue Date
7009423	Programmable I/O interfaces for FPGAs and other PLDs A programmable logic device (PLD), such as a field programmable gate array (FPGA) has a logic core surrounded on one or more sides by an input/output (I/O) interface having one or more programmable I/O buffers (PIBs). At least one PIB can be programmed to perform tw...	03/07/2006
7006387	Semiconductor memory device with adjustable I/O bandwidth A semiconductor memory device with adjustable I/O bandwidth includes a plurality of data I/O buffers connected one by one to a plurality of I/O ports, a switch array including a plurality of switches for connecting the plurality of data I/O buffers to a plurality of...	02/28/2006
7006396	Semiconductor memory device and precharge control method A semiconductor memory device that quickly precharges a bit line and shortens the cycle time for accessing the memory cells. The semiconductor memory device includes a memory cell array having a plurality of memory cells. A bit line is connected to the plurality of ...	02/28/2006
7002852	Data output circuits for synchronous integrated circuit memory devices A data output circuit includes a plurality of registers and a plurality of register output selection switches that are respectively connected to the plurality of registers. Pairs of the plurality of register output selection switches are connected by respective comm...	02/21/2006
7003713	Variable Hamming error correction for a one-time-programmable-ROM A one-time-programmable (OTP) module includes OTP memory and OTP input/output (I/O) that performs error correction operations. The OTP module may be used in a data communications system. The error correction operations operate according to one of a plurality of supp...	02/21/2006
7002983	Device for datastream decoding A device for data stream analyzing that is able to recognize different data streams and then start processors or functionalities to store or check data in a data stream. The device includes a processor means and a program memory, making it possible to parse a data s...	02/21/2006
7002860	Multilevel register-file bit-read method and apparatus A bit-read apparatus includes a first decoder and N multiplexers, each having Q output nodes and Q pull-ups coupled thereto. Respective multiplexers have M selectors coupled to N×M respective select lines and register-file cells. The selectors are in Q groups coupl...	02/21/2006
7002855	Leakage tolerant register file A register file includes a dynamic local bit trace, a plurality of data cells coupled to the dynamic local bit trace, and a device coupled to the dynamic local bit trace to facilitate precharging the dynamic local bit trace to a precharge value and to intelligently ...	02/21/2006
6999361	Method and apparatus for data compression in memory devices A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coupled to a pa...	02/14/2006
6996819	Method for efficiently downloading SCSI and SERVO firmware to SCSI target controllers A system and method for overcoming prior impediments to the downloading of microcode firmware to a target controller of a disk or tape storage unit where an Inquiry command determines the type of firmware required by the target controller while a selection means cho...	02/07/2006
6992930	Semiconductor memory device, method for driving the same and portable electronic apparatus A method for driving a semiconductor memory device includes a memory array having a plurality of memory cells arranged in rows and columns. Each memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region dispos...	01/31/2006
6985391	High speed redundant data sensing method and apparatus An apparatus and method for coupling a normal bit line pair and a second bit line pair onto a desired bit line pair are described. This method comprises driving the desired bit line pair to emulate the normal bit line pair during a read cycle. Additionally, if the s...	01/10/2006
6980453	Flash memory with RDRAM interface A flash memory has been described that has an interface corresponding to a rambus dynamic random access memory (RDRAM). The memory samples commands and addresses on a rising edge of a clock signal. The read and write data are provided on both the rising edge and the...	12/27/2005
6981175	Memory and method for employing a checksum for addresses of replaced storage elements A memory includes: a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address fuse units, each having a plurality of fusible links and being operable to store a replacement address, each replacement add...	12/27/2005
6981187	Test mode for a self-refreshed SRAM with DRAM memory cells A self-refreshing SRAM with internal DRAM memory cells is provided with a test mode enable circuit for testing the real refresh time of the internal SRAM memory cells and for determining the maximum refresh capability of the internal DRAM memory cells. The self-refr...	12/27/2005
6978408	Generating array bit-fail maps without a tester using on-chip trace arrays An existing trace array on a chip is used to store the locations of bit failures from the automatic self-testing of an SRAM array. If a system is having problems, a technician can trigger the automatic test and then scan the trace array, thereby locating a large num...	12/20/2005
6977852	ROM-based controller monitor in a memory device A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can...	12/20/2005
6975558	Integrated circuit device An integrated circuit device is disclosed. In one particular exemplary embodiment, the integrated circuit device may comprise a first circuit to receive, in a multiplexed format, control information and address information, wherein the control information specifies ...	12/13/2005
6976114	Method and apparatus for simultaneous bidirectional signaling in a bus topology A method and apparatus for providing bidirectional signaling in a bus topology is provided. The bus topology allows more than two electrical circuits or devices to be coupled together along one or more common electrical conductors. For each device on the bus, a tran...	12/13/2005
6975554	Method and system for providing a shared write driver A method for providing a shared write driver is provided. The method includes providing a write driver for a memory array. The memory array comprises a plurality of memory columns. The write driver is coupled to the plurality of memory columns. ...	12/13/2005
6973009	Semiconductor memory device capable of switching between an asynchronous normal mode and a synchronous mode and method thereof A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured to output a plurality of data in synchronism with the clock signal af...	12/06/2005
6973522	Microcomputer with program-revision ability A microcomputer has a ROM with pre-stored programs, a RAM storing a revision program for executing an interruption-processing, and a program counter in which an address is successively renewed during an execution of the ROM-stored programs. A first register stores a...	12/06/2005
6965539	Write path scheme in synchronous DRAM A write path scheme in a synchronous DRAM having: a data converter unit to convert serial input data to parallel output data, a multiplexer to output data from the data converter unit depending on a first mode selection signal and a second mode selection signal, and...	11/15/2005
6961831	Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one particular exemplary embodiment, the techniques may be realized through a memory system comprising a memory module and a memory controller. T...	11/01/2005
6959016	Method and apparatus for adjusting the timing of signals over fine and coarse ranges A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the...	10/25/2005
6958935	Nonvolatile semiconductor memory with X8/X16 operation mode using address control The present invention relates to a nonvolatile semiconductor memory, that is, a flash memory and especially to a NAND type flash memory device capable of selectively controlling data input/output units by an address control. In the NAND type flash memory device, a m...	10/25/2005
6956775	Write pointer error recovery A write pointer (21) from a write pointer circuit (13) may cause a demultiplexer circuit (12) to direct data from a memory cell (11A–11N) to a desired bit location (0–4) in a register 14. A read pointer (20) may c...	10/18/2005
6954097	Method and apparatus for generating a sequence of clock signals A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that ...	10/11/2005
6952462	Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ...	10/04/2005
6950772	Dynamic component to input signal mapping system A dynamic component to input signal mapping system is disclosed that receives different types of input signals applied to a number of components and provides resultant output signals. The system includes input ports receiving the input signals, output ports providin...	09/27/2005
6947350	Synchronous controlled, self-timed local SRAM block The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local contr...	09/20/2005
6948112	System and method for performing backward error recovery in a computer A system for performing data error recovery includes a memory unit and a memory controller. The memory unit includes a plurality of memory locations, and the memory controller maintains a checksum in one of the memory locations. At various times, the memory controll...	09/20/2005
6947305	Method for fabricating and identifying integrated circuits and self-identifying integrated circuits Two types of topologically different three-dimensional integrated circuits (for example a 4-layer three-dimensional memory array and an 8-layer three-dimensional memory array) are fabricated from a single set of photo-lithographic masks. In one example, masks 1-5 ar...	09/20/2005
6947340	Memory device for reducing skew of data and address A semiconductor memory device operates at a high speed regardless of variance of power voltage or process change, by consistently keeping variance of the skew between the transfer path of the address and the transfer path of internal operation of the memory device. ...	09/20/2005
6944040	Programmable delay circuit within a content addressable memory An apparatus having an output register coupled to a content addressable memory (CAM) array. The output register may be configured to output data based on a delayed clock signal. A programmable delay circuit may be coupled to receive a reference clock signal and gene...	09/13/2005
6940780	Flash array implementation with local and global bit lines A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a contr...	09/06/2005
6937493	Programming flash memory via a boundary scan register A method and parallel interface for on-board programming and/or In-System Configuration of a flash memory mounted on a printed circuit board by controlling its inputs with the aid of an ASIC mounted on the same circuit board via a Boundary Scan register of which the...	08/30/2005
6934183	Method and apparatus for resetable memory and design approach for same A resetable memory is described that includes a memory without reset capability having a data output coupled to a first input of a first multiplexer. A second input of the first multiplexer has a reset value input. A channel select for the first multiplexer is coupl...	08/23/2005
6930929	Simultaneous read-write memory cell at the bit level for a graphics display An improved memory for graphics displays includes an improved memory cell. Data may be written and read from the single bit cell simultaneously, eliminating the need for additional memory circuits to service an N column driver for a display. Additionally, the archit...	08/16/2005
6931086	Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ...	08/16/2005

«First «Previous 4 5 6 7 8 9 10 11 12 13 14 Next»Last»

PatentStorm

Bizarre Patents

PatentStorm News

Class 365/189.02 - Multiplexing