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| Number | Title | Issue Date |
| 4608678 | Semiconductor memory device for serial scan applications An improved semiconductor memory device for serial scan applications is presented. The semiconductor memory device as presented includes a main memory means combined with an on-board means for implementing a shift register function. The shift register fun... | 08/26/1986 |
| 4608667 | Dual mode logic circuit for a memory array An electronically selectable high performance data path switch which allows one input to drive two data buses or to have two inputs drive the two independently.... | 08/26/1986 |
| 4564926 | Information memory device with address multiplexing In an information memory device of the type wherein informations are sequentially stored in cells of a memory cell array and read out from the cells according to selected addresses, there are provided an internal address generator for generating an intern... | 01/14/1986 |
| 4558433 | Multi-port register implementations The present invention is especially directed towards an improved means for comparing the address inputs of word decoders in a memory array such that, when a compare occurs, selected ones of the array word decoders are disabled to prevent a multiple read, ... | 12/10/1985 |
| 4520464 | Transparent instruction word bus memory system A memory architecture for a single chip microprocessor or microcomputer in which instruction words have a greater bit length than the data words and the need exists for additional off-chip program memory. The instruction word lines from the off-chip progr... | 05/28/1985 |
| 4506348 | Variable digital delay circuit A variable digital delay circuit is disclosed which utilizes a shift register to periodically sample a signal to be delayed and after a predetermined number of samples are collected as a group of zeros and ones making up a binary word the word is stored i... | 03/19/1985 |
| 4450538 | Address accessed memory device having parallel to serial conversion A memory device is provided with first and second memories. Two groups of data are loaded into the first and second memories, through a data buffer register. The same address information is applied to the first and second memories and the information is r... | 05/22/1984 |
| 4449207 | Byte-wide dynamic RAM with multiplexed internal buses An MOS dynamic RAM organized in a byte-wide arrangement is described. An internal bus is used for multiplexed column address signals and data. Other multiplexing reduced the lines associated with the input/output circuits. A unique power-on circuit automa... | 05/15/1984 |
| 4447893 | Semiconductor read only memory device A semiconductor read only memory device comprises bit lines, word lines, a load transistor, a multiplexer including a plurality of transistors, and a memory cell array in which each memory cell has one transistor having a gate connected to one of the word... | 05/08/1984 |
| 4435792 | Raster memory manipulation apparatus An apparatus for manipulating and displaying raster images stored in a memory system under computer control, wherein a function unit combines new display data presented to the apparatus with display data already stored in memory, to form a new display tha... | 03/06/1984 |
| 4402067 | Bidirectional dual port serially controlled programmable read-only memory A bidirectional serially controlled programmable read-only memory has a serial input/output (I/O) port and a parallel I/O port. By selecting the appropriate control inputs, the instant invention can receive serial address or data information and output da... | 08/30/1983 |
| 4402065 | Integrated RAM/EAROM memory system An integrated circuit memory including a random memory (RAM) and a plurality of electrically alterable read only memories (EAROMS) having common controls. The data input for the RAM is either the system input or an EAROM and the data input for the EAROMS ... | 08/30/1983 |
| 4345319 | Self-correcting, solid-state-mass-memory organized by bits and with reconfiguration capability for a stored program control system A mass memory for use with telecommunication equipment comprises a plurality of memory units associated with respective controllers. Each memory unit includes a command module, dialoguing with the associated controller, and a multiplicity of memory module... | 08/17/1982 |
| 4339804 | Memory system wherein individual bits may be updated A memory system having a word-addressable memory and bit changing circuitry for changing or updating individual bits within the data words stored in the memory. The memory includes a primary memory and a copy memory. The copy memory stores duplicates of t... | 07/13/1982 |
| 4219883 | Cache memory control system Block information from a main memory, which is registered in an address register, is applied to a directory. A bank address in the main memory is taken out from the respective locations defined by the block information in each bank of the directory. A com... | 08/26/1980 |
| 4183058 | Video store A video data store including at least one storage device containing a plurality of storage elements together with input and output data latches. A queueing control receives write and read store commands and temporarily holds the command if a store cycle i... | 01/08/1980 |
| 4183095 | High density memory device A high density memory system is formed by reducing the number of electrical conductors that are needed to connect individual memory devices into an operable memory system. The reduction is accomplished by serially reading and writing data from and into se... | 01/08/1980 |
| 4120049 | Line memory In a character recognition system lines of data are stored in a line memory via a series of multiplexers. The data can originate in a controller for the system, a character reading station or other sub-systems, and is supplied to the line memory over a co... | 10/10/1978 |
| 4044330 | Power strobing to achieve a tri state Apparatus and a method for coupling and uncoupling data-read lines of a memory array to a data bus. The data read-out lines of a memory array which is comprised of any combination of latched or non-latched tri-state memories are coupled to the data bus ut... | 08/23/1977 |
| 3969706 | Dynamic random access memory misfet integrated circuit A MISFET dynamic random access memory chip having 4,096 single transistor, single capacitor storage cells yet packaged in a standard sixteen pin dual inline package is disclosed. Six bit row address and six bit column address data are sequentially multipl... | 07/13/1976 |
