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| Number | Title | Issue Date |
| 7619935 | Memory device with separate read and write gate voltage controls A circuit and method are provided for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the circuit including a local input/output line, a local from/to global input/output multiplexer in signal commu... | 11/17/2009 |
| 7606081 | Device programmable to operate as a multiplexer, demultiplexer, or memory device A device that is programmable to operate as a memory device, a multiplexer, or a demultiplexer includes: a first column decoder; a memory array coupled to the first column decoder; a plurality of selectors coupled to the memory array; and a second column decoder cou... | 10/20/2009 |
| 7590009 | Semiconductor memory apparatus and data masking method of the same A memory apparatus includes: a memory cell block; a data input part that performs signal processing to transmit general data and mask information input to the semiconductor memory apparatus to the memory cell block, and outputs the processed data and information; a ... | 09/15/2009 |
| 7580295 | Semiconductor memory device and memory system including semiconductor memory device A semiconductor memory device comprises a memory cell array comprising memory cells of a first type. The memory cell array performs write and read operations in response to signals designed for the operation of a memory cell array comprising memory cells of a type o... | 08/25/2009 |
| 7580294 | Semiconductor memory device comprising two rows of pads A semiconductor memory device includes a first row of pads including a first plurality of data input/output (I/O) pads; a second row of pads including a second plurality of data I/O pads; and a first I/O multiplexer associated with the first row of pads and providin... | 08/25/2009 |
| 7577038 | Data input/output multiplexer of semiconductor device There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a g... | 08/18/2009 |
| 7554857 | Data output multiplexer A data output multiplexer for multiplexing and transferring data of a data input/output (I/O) line includes a first latch unit coupled to the data I/O line to latch the data of the data I/O line, a transmission gate unit to transfer an output of the first latch unit... | 06/30/2009 |
| 7554858 | System and method for reducing pin-count of memory devices, and memory device testers for same Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output t... | 06/30/2009 |
| 7535772 | Configurable data path architecture and clocking scheme Data paths (100 and 900) can be configured to accommodate two or four burst data sequences, with a data value being input/output each half clock cycle. A data sequence can be a fixed order or user-defined order depending upon a selected option. A data ... | 05/19/2009 |
| 7529139 | N-port memory circuits allowing M memory addresses to be accessed concurrently and signal processing methods thereof Method and memory circuits capable of allowing M memory addresses of an N-port memory to be accessed concurrently, wherein N and M both are a natural number, and M is larger than N. Accordingly, a higher-order multi-port memory can be replaced by a lower-order multi... | 05/05/2009 |
| 7518933 | Circuit for use in a multiple block memory A portion of a memory may include a first memory block, including a first memory cell coupled to a first memory data line, a second memory block, including a second memory cell coupled to a second memory data line, and a latch, having a first terminal and a second t... | 04/14/2009 |
| 7512018 | Column address enable signal generation circuit for semiconductor memory device A semiconductor memory device includes a clock period detector, a column address enable signal generator, and a multiplexing circuit. The clock period detector detects a period of an external clock in response to a pulse width information signal having a pulse width... | 03/31/2009 |
| 7499340 | Semiconductor memory device and defect remedying method thereof A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and th... | 03/03/2009 |
| 7477551 | Systems and methods for reading data from a memory array One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series ... | 01/13/2009 |
| 7457169 | Flash with consistent latency for read operations A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device includes a pipelined buffer with selectable propagation paths to route data from the input co... | 11/25/2008 |
| 7447110 | Integrated circuit devices having dual data rate (DDR) output circuits therein A dual data rate (DDR) output circuit has first and second data paths therein that are asymmetric. The first data path is provided through a single-stage latch unit and the second data path is provided through a dual-stage flip-flop device containing a cascaded arra... | 11/04/2008 |
| 7440335 | Contention-free hierarchical bit line in embedded memory and method thereof A memory includes a plurality of lower level bit lines, a higher level bit line, and bit line driving circuitry. The bit line driving circuitry includes a plurality of bit line inputs, each bit line input coupled to a corresponding one of the plurality of lower leve... | 10/21/2008 |
| 7437500 | Configurable high-speed memory interface subsystem A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic rando... | 10/14/2008 |
| 7433980 | Memory of and circuit for rearranging the order of data in a memory having asymmetric input and output ports Circuits and methods of rearranging the order of data in a memory having asymmetric input and output ports are disclosed. According to one embodiment, a method comprises steps of providing an input port of a memory having an input width and output port having an out... | 10/07/2008 |
| 7430137 | Non-volatile memory cells in a field programmable gate array A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel... | 09/30/2008 |
| 7426144 | Semiconductor storage device A semiconductor storage device comprising: a transfer control circuit for prefetching data of a predetermined number of bits stored in a memory array in response to a read command, and transferring L bits of the prefetched data in parallel to an internal bus in sync... | 09/16/2008 |
| 7423917 | Data readout circuit of memory cells, memory circuit and method of reading out data from memory cells A data readout circuit of memory cells for reading out data from the memory cells includes a determination circuit (3) that reads out a plurality of data from multiplexed memory cells (5) having a unique data inversion direction and determines data not... | 09/09/2008 |
| 7420869 | Memory device, use thereof and method for synchronizing a data word The invention includes a memory device with a register device to which an output of a multiplexer is connected. The input of the multiplexer is connected to a buffer store. In addition, the memory device includes a synchronization circuit having a control output con... | 09/02/2008 |
| 7417888 | Method and apparatus for resetable memory and design approach for same A resetable memory is described that includes a memory without reset capability having a data output coupled to a first input of a first multiplexer. A second input of the first multiplexer has a reset value input. A channel select for the first multiplexer is coupl... | 08/26/2008 |
| 7414916 | Using dedicated read output path to reduce unregistered read access time for FPGA embedded memory A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read output paths for accessing data at the full data width of the memory arr... | 08/19/2008 |
| 7411844 | Semiconductor memory device having a redundancy information memory directly connected to a redundancy control circuit A semiconductor memory device (M) includes a memory array (MA) having a plurality of memory cells, a redundancy array (RA) having a plurality of memory cells, a non-volatile redundancy information memory (NVR) having a plurality of memory cells for storing redundanc... | 08/12/2008 |
| 7411839 | Data input circuit of semiconductor memory device and data input method thereof A data input circuit of a semiconductor memory device and a data input operating method thereof, in which data input margin can be secured. The data input circuit includes a strobe buffer that receives an external data strobe signal in response to a data input signa... | 08/12/2008 |
| 7408483 | Apparatus and method of generating DBI signal in semiconductor memory apparatus An apparatus for generating a DBI signal in a semiconductor memory apparatus includes a data switching detection unit that detects whether or not previous data is consistent with current data and outputs a detection signal according to a detection result, and a DBI ... | 08/05/2008 |
| 7405980 | Shared terminal memory interface A memory architecture for a disk drive system in which Synchronous Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) functions are provided on separate integrated circuits, and an interface protocol for transmitting information between these two me... | 07/29/2008 |
| 7405990 | Method and apparatus for in-system redundant array repair on integrated circuits Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit wit... | 07/29/2008 |
| 7403439 | Bitline leakage limiting with improved voltage regulation Circuit arrangements and methods are provided for regulating and maintaining voltage on bitlines of a semiconductor memory device. According to one embodiment, first and second regulation devices are connected to a charging circuit. At the beginning of a charging pe... | 07/22/2008 |
| 7403446 | Single late-write for standard synchronous SRAMs Synchronous SRAM may conform to Std. Sync or early-write at an external interface whilst providing late-write internally. ... | 07/22/2008 |
| 7400540 | Programmable memory and access method for the same A programmable memory includes N number of one-time programmable (OTP) memory rows, an output module, a judge module, and a write-in module. The output module receives all data of the OTP memory rows and generates output data. The judge module receives the output da... | 07/15/2008 |
| 7400548 | Method for providing multiple reads/writes using a 2read/2write register file array Reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file is provided. In one exemplary embodiment, a 64 entry register file array is partitioned into... | 07/15/2008 |
| 7400034 | Semiconductor device There is provided a large capacity memory such as a DRAM and an SDRAM n which bonding pads PS and PD are not located at the center, but are displaced from the center between memory array regions UL and UR, disposed on the upper side of a four-bank structure of banks... | 07/15/2008 |
| RE40423 | Multiport RAM with programmable data port configuration A RAM with programmable data port configuration provides for programmable configuration of RAM data ports, and in the case of a multiport RAM, for independent programmable configuration of each data port. A single programmable RAM cell can be utilized in a variety o... | 07/08/2008 |
| 7397709 | Method and apparatus for in-system redundant array repair on integrated circuits Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit wit... | 07/08/2008 |
| 7394681 | Column select multiplexer circuit for a domino random access memory array A column select multiplexer circuit for a domino random access memory array including a plurality of column selector circuits for selecting a column from a plurality of columns of static random access memory cells. ... | 07/01/2008 |
| 7391643 | Semiconductor memory device and writing method thereof To provide a semiconductor memory device comprising a phase-change memory and having high compatibility with DRAM interface. The memory cell array 18 comprises a memory cell that includes a phase-change element provided at the intersection of a bit line and w... | 06/24/2008 |
| RE40356 | Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells locate... | 06/03/2008 |
