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| Number | Title | Issue Date |
| 6850444 | Data input device of a DDR SDRAM A data input device of a DDR SDRAM includes at least a clock pulse generator (for outputting a data-in-strobe signal based on internal clock), first and second data buffers (being controlled by the data-in-strobe signal and having output lines corresponding to first... | 02/01/2005 |
| 6845048 | System and method for monitoring internal voltages on an integrated circuit A system and method for monitoring internal voltage sources in an integrated circuit, such as a DRAM integrated circuit, includes an internal analog multiplexing circuit, an internal analog-to-digital converter, and an interface circuit. Through the analog multiplex... | 01/18/2005 |
| 6845024 | Result compare circuit and method for content addressable memory (CAM) device A content addressable memory (CAM) device (100) may include a number of blocks (102-[n−1, n, n+1]) that each generate CAM search results and result compare circuits (104-[n−1, n, n+1] that receive CAM search resul... | 01/18/2005 |
| 6842815 | Output drivers preventing degradation of channel bus line in a memory module equipped with semiconductor memory devices including the output drivers Output drivers in semiconductor memory devices such as Rambus DRAM prevent degradation of the signal characteristics of a channel bus line in a memory module equipped with the semiconductor memory devices. Each semiconductor memory device includes blocks of memory c... | 01/11/2005 |
| 6834015 | Semiconductor memory device for reducing data accessing time A semiconductor memory device minimizes a data accessing time. For the purpose, it includes a first control signal generator for producing a first control signal by logically combining a pipelatch-in signal and a start-odd start-even data output control signal, a se... | 12/21/2004 |
| 6826657 | Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory system comprising a memory module and a memory controller. The memory modu... | 11/30/2004 |
| 6826110 | Cell circuit for multiport memory using decoder An improved cell circuit for data readout with reduced number of read wordlines is provided in a memory block of a multiport memory array. The number of read wordlines is significantly reduced by using a decoder between the read wordlines and a multiplexer in the ce... | 11/30/2004 |
| 6823441 | Method of multiplexed address and data bus A multiplexed addressed data bus are provided for transferring data between two microprocessors. The multiplexed address and data bus include a plurality of multiplexed lines for communicating between the two microprocessors. A read/write signal line is also provide... | 11/23/2004 |
| 6816420 | Column redundancy scheme for serially programmable integrated circuits A serially programmable integrated circuit (IC) includes a memory array and multiple data registers daisy-chained by bypass logic. Each of the data registers is associated with a primary column grouping or redundant column grouping in the memory array. If a data reg... | 11/09/2004 |
| 6816416 | Memory device having reduced layout area A memory device having a memory core, a local equalizer, and a local-global multiplexer. The memory core is connected to local input/output lines and global input/output lines. The local equalizer is configured to precharge the local input/output lines. The global m... | 11/09/2004 |
| 6813195 | Pipe latch circuit for outputting data with high speed It is an objective of the present invention to provide a pipe latch circuit with simpler control, smaller footprint, and higher speed operation. For this purpose, the present invention provides a pipe latch circuit for storing a sequentially received plurality of fi... | 11/02/2004 |
| 6813193 | Memory device and method of outputting data from a memory device A method of outputting data from a memory device, such as a dynamic random access memory, is disclosed. The method comprises the steps of providing an integrated circuit having a plurality of memory arrays; separately buffering data from separate memory arrays of th... | 11/02/2004 |
| 6813175 | Interconnection layout of a semiconductor memory device An interconnection layout includes alternately arranged data-read lines and data-write lines. The data-write lines are maintained at a ground voltage level when the data-read lines in a transitional state, and the data-read lines are maintained at the ground voltage... | 11/02/2004 |
| 6809970 | Input stage apparatus and method having a variable reference voltage Input stage having increased input signal noise margin and method for generating an output signal having a predetermined logic level based on the voltage level of an input signal. The input stage includes an input buffer generating an output signal having a logic le... | 10/26/2004 |
| 6809965 | Control circuitry for a non-volatile memory Control circuitry for applying voltages to a memory circuit. In accordance with this invention, row circuitry applies either a high voltage or a low voltage to a memory cell based on the operation to be performed and column circuitry applies a high or a low voltage ... | 10/26/2004 |
| 6809944 | CAM with automatic next free address pointer A method and apparatus for automatically providing a Next Free Address (NFA) within a Content Addressable Memory (CAM) is disclosed. The NFA can be determined simultaneously with a search process using a priority encoder for indicating a highest priority storage loc... | 10/26/2004 |
| 6807598 | Integrated circuit device having double data rate capability A synchronous integrated circuit device including a clock receiver to receive an external clock signal and a plurality of output drivers to output data. A first portion of the data is output synchronously with respect to a rising edge transition of the external cloc... | 10/19/2004 |
| 6804166 | Method and apparatus for operating a semiconductor memory at double data transfer rate A data read access and a data write access is shared between two memory banks. A first memory bank of which is operated with a clock that is shifted by half a clock pulse with respect to the operating clock of the other, second memory bank. Partial data streams are ... | 10/12/2004 |
| 6804155 | Semiconductor storage device A semiconductor storage device includes an array region, which includes memory cell array blocks and is connected to a (k: k is a natural number)-number of data input/output lines. A (k+m: m is a natural number)-number of common internal data lines are provided in c... | 10/12/2004 |
| 6795889 | Method and apparatus for multi-path data storage and retrieval A means and method to receive and store a continuous flow of data items being processed in a data processing system in which data items are received from multiple sources simultaneously. The invention provided for simultaneous retrieval of previously stored data fro... | 09/21/2004 |
| 6791889 | Double data rate memory interface A system supports Double Date Rate (DDR) or Single Data Rate (SDR) data transfers on a data bus between a processor and a memory device. A controller-side interface block connects to a memory-side interface block for generating the control signals and transferring s... | 09/14/2004 |
| 6788613 | Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (r·s·t) memory locations with the memory array organized as a first memory sub... | 09/07/2004 |
| 6785782 | Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory module for storing data thereon. The memory module comprises a memory comp... | 08/31/2004 |
| 6785185 | Semiconductor memory device, information apparatus, and method for determining access period for semiconductor memory device A semiconductor memory device comprises first and second memory sections including a plurality of memory elements, and a memory control section for allowing a data transfer operation between the first and second memory sections based on an external control command w... | 08/31/2004 |
| 6785168 | Semiconductor memory device having advanced prefetch block A semiconductor memory device includes an advanced prefetching block for prefetching more bit data at once and effectively arranging the prefetched data so as to reduce an address access time of the semiconductor memory device. The semiconductor memory device having... | 08/31/2004 |
| 6779075 | DDR and QDR converter and interface card, motherboard and memory module interface using the same A DDR and QDR converter and an interface, a motherboard and a memory module interface using the same. The DDR and QDR converter has a QDR interface, a DDR interface and a conversion core. The QDR interface is used to exchange a signal with QDR devices. The DDR inter... | 08/17/2004 |
| 6778431 | Architecture for high-speed magnetic memories A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable a... | 08/17/2004 |
| 6775193 | System and method for testing multiple embedded memories The present invention provides a system and method for testing embedded memories. The present invention logically combines many different embedded memories into one or more large, virtual memory blocks in order to test multiple memories together. The invention defin... | 08/10/2004 |
| 6768684 | System and method for small read only data A system and method is provided for minimizing read-only data retrieval time and/or area through the use of combinatorial logic. In one embodiment of the present invention, two address bits are provided to a binary logic function device. The binary logic function de... | 07/27/2004 |
| 6760260 | Semiconductor memory apparatus A semiconductor memory apparatus includes a memory cell array having a multiplicity of data lines and a multiplicity of local amplifiers, each of the local amplifiers being associated with a data line. An amplifier group includes at least two amplifiers selected fro... | 07/06/2004 |
| 6757209 | Memory cell structural test An apparatus and method for testing memory cells comprising coupling a first and a second memory cell to a first and a second bit lines, respectively, reading data from the first and second memory cells through the first and second bit lines, and comparing the volta... | 06/29/2004 |
| 6741518 | Semiconductor integrated circuit device and data writing method therefor Provided is a semiconductor integrated circuit device capable of, when data is written into a memory cell, fixing adjacent complimentary bit lines to a predetermined voltage, thereby reducing an effect of a write noise for a readout operation of the adjacent cells, ... | 05/25/2004 |
| 6741497 | Flash memory with RDRAM interface A flash memory has been described that has an interface corresponding to a rambus dynamic random access memory (RDRAM). The memory samples commands and addresses on a rising edge of a clock signal. The read and write data are provided on both the rising edge and the... | 05/25/2004 |
| 6724669 | System and method for repairing a memory column A system for repairing a memory column includes a multiplexer operable to receive a first data bit and a second data bit. The multiplexer is operable to select one of the first data bit and the second data bit. The system also includes a control generator operable t... | 04/20/2004 |
| 6721202 | Bit encoded ternary content addressable memory cell Architecture, circuitry and method are provided for a ternary content addressable memory (TCAM), and use thereof. Each TCAM cell is relatively small in size. If the TCAM cell is called upon to store voltage values indefinitely, provided power is retained on the cell... | 04/13/2004 |
| 6721233 | Circuit and method for reducing memory idle cycles An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Becau... | 04/13/2004 |
| 6721212 | Memory control circuit and control system for a plurality of memories interconnected via plural logic interfaces A memory control circuit includes a controller (1A) for controlling a RAM (13) conforming to the standard where source voltage is 2.5 V (SSTL2 standard), and a nonvolatile memory (14) conforming to the standard where source voltage is 3.3 V (LVT... | 04/13/2004 |
| 6717885 | Switching circuit capable of improving memory write timing and method thereof In DRAM system where quad rate transmission is used, at least one latch is disposed within a switching circuit for increasing the data valid windows of a portion of transmitted data segments. For example, in a sequence of transmitted data segments, only the odd numb... | 04/06/2004 |
| 6717882 | Cell circuit for multiport memory using 3-way multiplexer An improved cell circuit for data readout for use in a multiport memory is provided. The multiport memory stores write data signals. The cell circuit includes a plurality of multiplexers each coupled to a discharge device. Each of the multiplexers receives a subset ... | 04/06/2004 |
| 6714466 | System of performing a repair analysis for a semiconductor memory device having a redundant architecture Two temporary buffers are employed alternatively storing a fail address data designated from a test operation, in which one of the temporary buffers transfers the fail address data to a data buffer in order to perform a repair analysis while the other one is storing... | 03/30/2004 |
