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"I watched his countenance closely, to see if he was not deranged ... and I was assured by other senators after he left the room that they had no confidence in it."
U.S. Senator Smith of Indiana ; After seeing Samuel Morse demonstrate the telegraph.
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| Number | Title | Issue Date |
| 7200063 | Circuitry for a programmable element As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage sour... | 04/03/2007 |
| 7200778 | System and method for verifying HDL events for observability In one embodiment, the invention is directed to a method of verifying conditions occurring during a simulation of a hardware design. The method comprises logging each occurrence of at least one specified condition in a first log; logging signals observed at an obser... | 04/03/2007 |
| 7197611 | Integrated circuit memory device having write latency function A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or... | 03/27/2007 |
| 7196963 | Address isolation for user-defined configuration memory in programmable devices In one embodiment of the invention, a block of configuration memory has rows of memory cells, at least one row having a set of one or more dual-port memory cells adapted to selectively store either configuration data or local data. The configuration address line for... | 03/27/2007 |
| 7196939 | Method for controlling precharge timing of memory device and apparatus thereof A method for controlling a precharge timing of a memory device is disclosed. The method includes making timing of generation of a signal for determining a precharge timing in a normal operation and a signal for determining a precharge timing in a refresh operation d... | 03/27/2007 |
| 7196924 | Method of multi-level cell FeRAM Disclosed are use methods, integrated circuits, and manufacturing methods for ferroelectric memory. A data value from multiple data values is received, for example by a state machine controlling the ferroelectric memory. The different data values correspond to diffe... | 03/27/2007 |
| 7193898 | Compensation currents in non-volatile memory read operations Shifts in the apparent charge stored on a floating gate of a non-volatile memory cell can occur because of coupling of an electric field based on the charge stored in adjacent floating gates. The shift in apparent charge can lead to erroneous readings by raising the... | 03/20/2007 |
| 7193903 | Method of controlling an integrated circuit capable of simultaneously performing a data read operation and a data write operation A method of controlling an integrated circuit (IC) capable of simultaneously performing a data read operation and a data write operation is provided. The method comprises (a) receiving a write address, a read address, and write data, (b) determining, a memory block ... | 03/20/2007 |
| 7193885 | Radiation tolerant SRAM bit In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the... | 03/20/2007 |
| 7193904 | Random access memory with stability enhancement and early read elimination A random access memory includes a memory cell having an access device. The access device is switched on or off in accordance with a signal on a wordline to conduct a memory operation through the access device. A logic circuit is coupled to the wordline to delay or g... | 03/20/2007 |
| 7193913 | Sense amplifier circuit and read/write method for semiconductor memory device A sense amplifier circuit comprising a local I/O line pair, a global I/O line pair, a write amplification unit for amplifying and transferring data output from the global I/O line pair to the local I/O line pair in response to a first control signal, and a read ampl... | 03/20/2007 |
| 7193893 | Write once read only memory employing floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 03/20/2007 |
| 7193905 | RRAM flipflop rcell memory generator An RRAM flip-flop rcell memory of the type having a write address decoder, a read address decoder, a set of n flip flops, one AND gate associated with each flip flop in the set, a set of w OR gates where each of the w OR gates in the set has n inputs, the improvemen... | 03/20/2007 |
| 7193927 | Memory device and method having banks of different sizes A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of columns of memory cells are contained in each of the four banks. The bank in which an item of data are stored i... | 03/20/2007 |
| 7193894 | Clock synchronized nonvolatile memory device A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives comm... | 03/20/2007 |
| 7190284 | Selective lossless, lossy, or no compression of data based on address range, data type, and/or requesting agent An integrated memory controller (IMC) including MemoryF/X Technology which includes data compression and decompression engines for improved performance. The memory controller (IMC) of the present invention preferably selectively uses a combination of lossless, lossy... | 03/13/2007 |
| 7190603 | Nonvolatile memory array organization and usage A non-volatile semiconductor storage device array organization for wide program operations is achieved. The device includes a memory cell array region in which a plurality of C columns and R rows of memory cells comprise one UNIT, arranged in a “diffusion bit” a... | 03/13/2007 |
| 7187593 | Control system; control apparatus; storage device and computer program product A reading/writing process control unit for instructing a reading/writing process and an erasing process control unit for instructing an erasing process are provided separately and each is connected with two HDDs via a switch. While the reading/writing process contro... | 03/06/2007 |
| 7187592 | Multi-state memory Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full anal... | 03/06/2007 |
| 7185440 | Sensing contact probe A sensing contact probe includes a beam support and a probe. The probe has a bent beam body that extends from the beam support to a probe tip face that has a position and faces in an angular direction. The bent beam body has first and second beam layers bonded toget... | 03/06/2007 |
| 7187581 | Semiconductor memory device and method of operating same There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this ... | 03/06/2007 |
| 7187587 | Programmable memory address and decode circuits with low tunnel barrier interpoly insulators Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the ou... | 03/06/2007 |
| 7187613 | Method and apparatus for dynamically configuring redundant area of non-volatile memory A method and an apparatus for dynamically configuring the redundant areas of a non-volatile memory is provided wherein each page of a memory is configured into a plurality of data areas and a plurality of redundant areas. The redundant areas interleave the data area... | 03/06/2007 |
| 7184344 | Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one ... | 02/27/2007 |
| 7185208 | Data processing In one embodiment of the present invention, there is disclosed a reversible method of processing data comprising the data being encrypted before being written to a non-volatile memory wherein the data cannot be accessed without decryption in the case of a direct phy... | 02/27/2007 |
| 7184346 | Memory cell sensing with low noise generation Various methods, apparatuses and systems in which a memory uses a noise reduction circuit to sense groups of memory cells. The memory has a plurality of memory cells organized into groups of memory cells. The noise reduction circuit performs a sense operation on a f... | 02/27/2007 |
| 7184295 | Memory device A memory device is provided in which recording of multi-valued data can be performed at a high speed and the recording of multi-valued data can be performed with a drive circuit having comparatively simple configuration. The memory device is formed of a memor... | 02/27/2007 |
| 7184341 | Method of data flow control for a high speed memory A new method of increasing access cycle time in a memory device is achieved. The memory device has three operating states of standby, read, and write. The data lines in the memory device may be pre-charged. The method comprises, first, during the standby state, the ... | 02/27/2007 |
| 7185271 | Methods and systems for implementing auto-complete in a web page A computer-implemented method for facilitating auto-completion of user data input in a web page. The method includes receiving, during execution time of the web page, first user data input in a first data input field of the web page. The method also includes analyzi... | 02/27/2007 |
| 7184290 | Logic process DRAM A dynamic random access memory (DRAM) unit includes pluralities of bit line pairs and word lines. Each bit line pair includes first and second bit lines aligned with each other in an end-to-end arrangement. The first bit lines are arranged substantially parallel and... | 02/27/2007 |
| 7184323 | 4N pre-fetch memory data transfer system A semiconductor storage device has a data transfer circuit capable of reducing the latency, including a control circuit for frequency-dividing external clock signal to generate readout clocks, first to fourth amplifier circuits for amplifying read data corresponding... | 02/27/2007 |
| 7184856 | System and method for smart card personalization A smart card personalization system maintains a database containing card issuer data format templates, card applications, card operating system commands, and personalization equipment specifications and provides a centralized interface of inputs and outputs to a car... | 02/27/2007 |
| 7180768 | Semiconductor memory device including 4TSRAMs Disclosed is a method of improving stability of a memory cell in read mode in an SRAM including a memory cell comprising two access MOS transistors and two drive MOS transistors. The magnitude of voltage between gate and source of an access transistor of a memory ce... | 02/20/2007 |
| 7180790 | Non-volatile memory device having controlled bulk voltage and method of programming same Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device is programmed by applying a wordline voltage, a bitline voltage, and a bulk voltage to memory cells within the device. During a programming operation for t... | 02/20/2007 |
| 7181067 | Efficient method and system for determining parameters in computerized recognition In computerized recognition having multiple experts, a method and system is described that obtains an optimum value for an expert tuning parameter in a single pass over sample tuning data. Each tuning sample is applied to two experts, resulting in scores from which ... | 02/20/2007 |
| 7180798 | Semiconductor physical quantity sensing device A semiconductor physical quantity sensing device to perform electrical trimming at low cost by using a CMOS manufacturing process and a small number of terminals. The semiconductor physical quantity sensing device includes a wheatstone bridge circuit, which is a sen... | 02/20/2007 |
| 7181497 | Messaging application user interface for auto-completing address text and modifying the auto-completion behavior A messaging application user interface has an input element for receiving electronic messages and an output element for displaying electronic messages. The messaging application user interface can be implemented so as to maintain a subset of the plurality of potenti... | 02/20/2007 |
| 7177201 | Negative bias temperature instability (NBTI) preconditioning of matched devices An accumulated data-dependent post-manufacture shift in a characteristic of one or more of a pair of matched devices within an integrated circuit may cause a mismatch in the characteristic between the pair of matched devices. This mismatch may be reduced by precondi... | 02/13/2007 |
| 7178102 | Representing latent data in an extensible markup language document Methods and systems allow style and other formatting settings to remain latent until one or more particular style or formatting settings is instantiated by a user. Data representing each latent style or formatting object is persisted in a data structure apart from t... | 02/13/2007 |
| 7177223 | Memory device and method having banks of different sizes A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of columns of memory cells are contained in each of the four banks. The bank in which an item of data are stored i... | 02/13/2007 |
