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Felix Hoffmann, a German chemist, was searching for something to relieve his father's arthritis. In doing so, he "rediscovered" acetylsalicylic acid and in 1900, patented a stable process for developing it. Hence, we have aspirin.
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| Number | Title | Issue Date |
| 7281090 | Data managing method for memory apparatus A block correlation table includes block addresses of unusable block portions in an irreversibly writeable memory and includes addresses of associated substitute block portions in the irreversibly writeable memory. A request for data stored at a logical address is r... | 10/09/2007 |
| 7280417 | System and method for capturing data signals using a data strobe signal A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the... | 10/09/2007 |
| 7280416 | Nonvolatile memory system The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emerge... | 10/09/2007 |
| 7280410 | System and method for mode register control of data bus operating mode and impedance A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signa... | 10/09/2007 |
| 7280398 | System and memory for sequential multi-plane page memory operations A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for a... | 10/09/2007 |
| 7280405 | Integrator-based current sensing circuit for reading memory cells Near-ground sensing of non-volatile memory (NVM) cells is performed on a selected NVM cell by applying a potential to a first terminal, coupling a second terminal to ground, and then decoupling the second terminal and passing the resulting cell current to an integra... | 10/09/2007 |
| 7281245 | Mechanism for downloading software components from a remote source for use by a local software application A method and system are provided for downloading software components from a remote source to a software application for providing updates or additions to the application's functionality. All components and files that may be utilized to update or add to functionality... | 10/09/2007 |
| 7277320 | Magnetic memory device, sense amplifier circuit and method of reading from magnetic memory device A magnetic memory device and a sense amplifier circuit capable of obtaining a read signal output with a high S/N ratio and reducing power consumption and a circuit space, and a method of reading from a magnetic memory device are provided. In a sense amplifier, trans... | 10/02/2007 |
| 7277330 | Nonvolatile semiconductor memory device having improved redundancy relieving rate In a memory cell array of an MRAM, a normal memory cell is compared with a reference memory cell which holds a reference value, thereby storing data of one bit per cell. Two spare memory cells store data of one bit as a whole. By writing complementary values to the ... | 10/02/2007 |
| 7277323 | Non-volatile semiconductor memory A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the ... | 10/02/2007 |
| 7277332 | Method and circuit for elastic storing capable of adapting to high-speed data communications A buffer circuit includes a plurality of registers, a write register selector, a read register selector, and an address proximity detector. The write register selector operates in synchronism with a write clock signal and outputs write enable signals in a predetermi... | 10/02/2007 |
| 7277356 | Methods of controlling memory modules that support selective mode register set commands A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrat... | 10/02/2007 |
| 7275686 | Electronic equipment point-of-sale activation to avoid theft In accordance with an embodiment of the present invention, an electronic device is displayed for purchase by a user and includes a controller and a protected area for storing a key and a bar code associated with and for identifying the device including a password un... | 10/02/2007 |
| 7277308 | High performance and low area write precharge technique for CAMs A technique to pre-charge a CAM block array that includes a plurality of CAM blocks that is organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group... | 10/02/2007 |
| 7277353 | Register file In one embodiment, a memory circuit comprises one or more first memory cells, each of the one or more first memory cells configured to store at least one bit; one or more second memory cells, each of the one or more second memory cells configured to store at least o... | 10/02/2007 |
| 7274590 | Random access memory with stability enhancement and early read elimination A random access memory includes a memory cell having an access device. The access device is switched on or off in accordance with a signal on a wordline to conduct a memory operation through the access device. A logic circuit is coupled to the wordline to delay or g... | 09/25/2007 |
| 7275130 | Method and system for dynamically operating memory in a power-saving error correcting mode A scrubbing controller used with a DRAM stores data in an error correcting code format. The system then uses a memory control state machine and associated timer to periodically cause the DRAM to read the error correcting codes. An ECC generator/checker in the scrubb... | 09/25/2007 |
| 7274220 | Method and apparatus for amplifying a regulated differential signal to a higher voltage A sense amplifier for use in a memory device and in a memory-resident system. The sense amplifier operates on a lower voltage consistent with the voltage range of the differential input data and the sense amplifier further operates on a higher voltage to level-shift... | 09/25/2007 |
| 7272061 | Dynamic pre-charge level control in semiconductor devices Dynamic control of a pre-charge level particularly for memory cells is described. In one example, a circuit block has pre-charge node and a power supply is coupled to the pre-charge node to provide either a first power level or a second power level when the circuit ... | 09/18/2007 |
| 7269090 | Memory access with consecutive addresses corresponding to different rows A memory system (200) has an array of addressable storage elements (210) arranged in a plurality of rows and a plurality of columns, and decoding circuitry (220, 230) coupled to the array of addressable storage elements (210). The decodin... | 09/11/2007 |
| 7269699 | Method and memory system having mode selection between dual data strobe mode and single data strobe mode with inversion A memory system and a method of reading and writing data to a memory device selectively operate in both a single DQS mode with data inversion, and in a dual DQS mode. The device and method employ data strobe mode changing means for selectively changing operation of ... | 09/11/2007 |
| 7268023 | Method of forming a pseudo SOI substrate and semiconductor devices The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the ... | 09/11/2007 |
| 7269077 | Memory architecture of display device and memory writing method for the same A memory architecture of display device comprises a memory cell array having a plurality of memory cells arranged as a plurality of cell rows and a plurality of cell columns, and a data latch circuit having a plurality of latch units for storing a plurality of bits;... | 09/11/2007 |
| 7266009 | Ferroelectric memory For a predetermined period from the start of a read operation, an electric current is fed to bit lines connected with memory cells so that ferroelectric capacitors of the memory cells are charged. The voltage change of the bit lines are different according to the lo... | 09/04/2007 |
| 7266039 | Circuitry and method for adjusting signal length A circuit for adjusting a signal length is adapted for a memory device. The circuit adjusts a signal length of an ATD signal. The circuit includes a timing module, an encoding module and a logical control unit. Wherein, the timing module generates a plurality of tim... | 09/04/2007 |
| 7263591 | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile m... | 08/28/2007 |
| 7262985 | Memory A memory capable of easily setting a reference potential and correctly determining data is provided. This memory comprises a ferroelectric capacitor holding data, and a driving line and a data line linked with the ferroelectric capacitor. The memory applies a voltag... | 08/28/2007 |
| 7263007 | Semiconductor memory device using read data bus for writing data during high-speed writing A semiconductor device is provided that can perform simultaneous writing of a large number of bits, without an increase in chip size. This semiconductor device includes: a write data bus via which data are written into memory cells; a read data bus via which the dat... | 08/28/2007 |
| 7263018 | Compensating a long read time of a memory device in data comparison and write operations A memory device is disclosed that has a longer read time than write time and implements a parallel-read operation. The parallel-read operation saves reading time and thus accelerates a write operation that comprises a step of comparing incoming data with memory data... | 08/28/2007 |
| 7259998 | Method for controlling memories of a plurality of kinds and circuit for controlling memories of a plurality of kinds It is made possible to control RAMs of a plurality of kinds differing in control system by using a single memory controller (LSI). A memory control circuit having an LSI configuration receives a RAM access request signal, which does not depend on a classification of... | 08/21/2007 |
| 7260015 | Memory device and method having multiple internal data buses and memory bank interleaving A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The downstream bus is coupled to a pair of internal write data buses, and the upstream bus is coupled to a pair of int... | 08/21/2007 |
| 7260020 | Synchronous global controller for enhanced pipelining The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller ... | 08/21/2007 |
| 7259989 | Non-volatile memory device A non-volatile memory device is disclosed that can reduce the time required for the initialization process. A non-volatile memory device includes a non-volatile memory array having a plurality of pages. Each page includes a plurality of non-volatile memory cells, a ... | 08/21/2007 |
| 7257023 | Hybrid non-volatile memory device The present invention discloses a memory device that includes a first memory cell array for storing one or more codes; a second memory cell array for storing one or more data, which are updated substantially more frequently than the codes; and a third memory cell ar... | 08/14/2007 |
| 7257041 | Memory circuit and related method for integrating pre-decoding and selective pre-charging In a memory circuit, memory cells are arranged in a matrix by “row line-and column line” (may also denoted as “word line and bit line”). The invention provides a memory circuit and related method capable for independently pre-charging the column lines or bit... | 08/14/2007 |
| 7257030 | Operating a storage component The invention relates to a method of operating a storage component 10, 30, 40. In order to enable a verification of the integrity of the data in the storage component, it is proposed that first a write operation for storing data in a data storage area 11, ... | 08/14/2007 |
| 7254724 | Power management system According to one embodiment of the present invention, there is provided a power management system for use in a computer system having a memory system incorporating a non-volatile memory and a controller which presents the logical characteristics of a disc storage de... | 08/07/2007 |
| 7254758 | Method and apparatus for testing circuit units to be tested with different test mode data sets The invention provides a test apparatus for testing a circuit unit to be tested. In one embodiment, a circuit unit incorporating aspects of the invention includes a data memory bank (106) for storing test mode data which are fed via an address control termina... | 08/07/2007 |
| 7254063 | Non-volatile semiconductor memory device and method for reading the same In a reference cell 202, first and second cells 50 and 52 having the same structure as that of a memory cell are provided. A memory cell current IREF1 of the first cell 50 is set to be a minimum value of a memory cell current after... | 08/07/2007 |
| 7254668 | Method and apparatus for grouping pages within a block Methods and apparatus for efficiently enabling pages within a block to be accessed are disclosed. According to one aspect of the present invention, a method for writing data into a first block in a non-volatile memory which includes pages that are grouped into group... | 08/07/2007 |
