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| Number | Title | Issue Date |
| 7158421 | Use of data latches in multi-phase programming of non-volatile memories A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells... | 01/02/2007 |
| 7158429 | System for read path acceleration A system for read path acceleration has a first strobe reset circuit coupled to a first local amplifier. A second strobe reset circuit is coupled to a second local amplifier. A main amplifier is coupled to an output of the first local amplifier and an output of the ... | 01/02/2007 |
| 7158442 | Flexible latency in flash memory A method of reading data in and outputting data from a memory structure includes a buffer. In the present method, first read operation is undertaken to read a first set of data in the memory structure and provide data of the first set of data to the buffer, using an... | 01/02/2007 |
| 7155561 | Method and system for using dynamic random access memory as cache memory A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs s... | 12/26/2006 |
| 7155581 | Method and apparatus for an energy efficient operation of multiple processors in a memory A method of operating a digital computer includes the steps of addressing a memory, reading a row of data from the memory, providing the same computational instruction simultaneously to each processor element of a plurality of processor elements, where each of the p... | 12/26/2006 |
| 7154770 | Bitcell having a unity beta ratio In one embodiment, the present invention includes a memory device formed of a latch device that includes a pair of pull-up transistors and a pair of pull-down transistors to store data, and a pair of wordline transistors coupled between a wordline and the latch devi... | 12/26/2006 |
| 7155357 | Method and apparatus for detecting an unused state in a semiconductor circuit An unused state detection circuit is disclosed that detects an unused state in a semiconductor circuit. A semiconductor circuit is “unused” when the unused state detection circuit has not been permanently cleared. When a semiconductor circuit is first powered up... | 12/26/2006 |
| 7155559 | Flash memory architecture with separate storage of overhead and user data A flash memory system segregates overhead data from user data so that overhead data may be addressed, programmed and erased independently from user data. The non-volatile memory medium of a flash memory system is mapped into a plurality of separately addressable mem... | 12/26/2006 |
| 7154140 | Write once read only memory with large work function floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 12/26/2006 |
| 7151707 | Memory device and method having data path with multiple prefetch I/O configurations A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel t... | 12/19/2006 |
| 7151704 | Semiconductor memory device Provided are a memory cell array, a column gate array, a row decoder, a column decoder, a sense amplifier array, a read data bus, an output buffer, and a redundancy discrimination signal bus. In the case of redundancy replacement, the output buffer outputs read data... | 12/19/2006 |
| 7152213 | System and method for dynamic key assignment in enhanced user interface An improved user interface for data input without the use of a standard keyboard is provided. Input is accepted through a data entry means such as a shuttle control system, a standard telephone keypad, or a speech recognition system. The data that is entered is sele... | 12/19/2006 |
| 7151703 | Semiconductor memory device including global IO line with low-amplitude driving voltage signal applied thereto A semiconductor memory device including a global IO line with a low-amplitude driving voltage signal applied thereto. In the device, a first driver converts a data signal of a first voltage level from a memory cell to a second voltage level in response to a read con... | 12/19/2006 |
| 7151701 | Self-adaptive program delay circuitry for programmable memories A self-adaptive programming circuit for EEPROM is used to automatically tune an erase or write delay, providing an improved programming window. The programming circuit may also provide improvements in data retention for programmed memory cells. The invention can be ... | 12/19/2006 |
| 7151709 | Memory device and method having programmable address configurations A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, addr... | 12/19/2006 |
| 7151687 | Ferroelectric memory device, electronic apparatus and driving method A ferroelectric memory device that is equipped with a cell array provided with a plurality of memory cells each having a first ferroelectric capacitor and a second ferroelectric capacitor that are connected to each other in series, a memory cell selection section th... | 12/19/2006 |
| 7151698 | Integrated charge sensing scheme for resistive memories An integrated charge sensing scheme for sensing the resistance of a resistive memory element is described. The current through a resistive memory cell is used to charge a capacitor coupled to a digit line. The voltage on the capacitor, which corresponds to the volta... | 12/19/2006 |
| 7147167 | Update management for encoded data in memory This invention concerns a system to update encoded data stored in a memory of a data processing device such as a smartcard. In this system, the data is represented by a tree structure in directories and files according to an object representation. According to the i... | 12/12/2006 |
| 7148503 | Semiconductor device, function setting method thereof, and evaluation method thereof The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs... | 12/12/2006 |
| 7149970 | Method and system for filtering and selecting from a candidate list generated by a stochastic input method A computer-implemented method and system for correcting text input from a stochastic input source is provided. After a text component such as a word or phrase is identified as erroneous where, for example, the stochastic input source translated the input incorrectly... | 12/12/2006 |
| 7149123 | Non-volatile CMOS reference circuit A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a reference NVM transistor, wherein a first voltage is appli... | 12/12/2006 |
| 7149130 | Page buffer circuit of flash memory device with reduced consumption power A page buffer circuit of a flash memory device has small consumption power. The page buffer circuit utilizes different voltages are supplied to the latch circuits in the standby and normal modes to reduce consumption power in the standby mode. ... | 12/12/2006 |
| 7149827 | Methods and apparatus for tristate line sharing Methods and apparatus are provided for interconnecting on-chip components, such as components on a programmable chip, with off-chip components through a variety of buses, fabrics, and input/output lines. Interconnection resources such as input/output lines are share... | 12/12/2006 |
| 7149109 | Single transistor vertical memory gain cell A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated... | 12/12/2006 |
| 7145819 | Method and apparatus for integrated circuit with DRAM Various aspects of an integrated circuit having a DRAM are disclosed. In one embodiment an integrated circuit includes a DRAM that (1) pre-charges the bit lines to a voltage that is biased toward a weaker one of two memory cell logic states, (2) selectively stores d... | 12/05/2006 |
| 7146454 | Hiding refresh in 1T-SRAM architecture A method and device for handling the refresh requirements of a DRAM or 1-Transistor memory array such that the memory array is fully compatible with an SRAM cache under all internal and external access conditions. This includes full compatibility when sequential ope... | 12/05/2006 |
| 7146456 | Memory device with a flexible reduced density option A dynamic random access memory device is capable of converting from a full density memory device to a reduced density memory device. The reduced density memory device compensates for cell failures in a plurality of cell blocks, regardless of the location of the cell... | 12/05/2006 |
| 7142461 | Active termination control though on module register A method and apparatus are provided for active termination control in a memory by a module register providing an active termination control signal to the memory. The module register monitors a system command bus for read and write commands. In response to detecting ... | 11/28/2006 |
| 7143157 | Managing the network impact of a digital transmitter Management of the network impact caused by a digital transmitter, such as a multifunction peripheral (an MFP), delays file transmission until available network bandwidth is sufficient to prevent adverse network impact. In one implementation, a resource determination... | 11/28/2006 |
| 7139196 | Sub-volt sensing for digital multilevel flash memory A digital multibit non-volatile memory integrated system includes autozero multistage sensing. One stage may provide local sensing with autozero. Another stage may provide global sensing with autozero. A twisted bitline may be used for array arrangement. Segment ref... | 11/21/2006 |
| 7139202 | Semiconductor storage device, mobile electronic apparatus, and method for controlling the semiconductor storage device A semiconductor storage device is provided, which comprises a memory array comprising memory elements, a write state machine for applying a first voltage for performing a write or erase operation, with respect to one of the memory elements, to the memory element via... | 11/21/2006 |
| 7139214 | Semiconductor integrated circuit An apparatus and method to reduce, during standby time, electric power caused by the leakage current flowing through a storage transistor in a 3-transistor dynamic cell. Source electrodes of storage transistors in a plurality of 3-transistor dynamic cells constituti... | 11/21/2006 |
| 7139183 | Logical arrangement of memory arrays An aspect of the present invention is a logical arrangement of memory arrays. The logical arrangement includes a plurality of memory arrays deposed in a row-column configuration, a controller coupled to the plurality of memory arrays and at least one power line, at ... | 11/21/2006 |
| 7139852 | Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing A method and system transfer read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations of the memory device. The method includes placing a sequence of read data words on the data bus and apply... | 11/21/2006 |
| 7137024 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 11/14/2006 |
| 7136319 | Reduced area, reduced programming voltage CMOS eFUSE-based scannable non-volatile memory bitcell An integrated circuit chip includes a number of memory bitcells. Each bitcell includes: a latch having a sense node; a programming transistor having an efficient saturation region of operation; and a fuse connected to the programming transistor at a first terminal o... | 11/14/2006 |
| 7135734 | Graded composition metal oxide tunnel barrier interpoly insulators Structures and methods for programmable array type logic and/or memory devices with graded composition metal oxide tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include a floating gate transistor. The float... | 11/14/2006 |
| 7136308 | Efficient method of data transfer between register files and memories A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass gate, at least one driver and a bit line. The at least one pass gate and... | 11/14/2006 |
| 7133308 | Memory device A memory device is provided in which recording of multi-valued data can be performed at a high speed and the recording of multi-valued data can be performed with a drive circuit having comparatively simple configuration. The memory device is formed of a memor... | 11/07/2006 |
| 7134057 | Off-pitch column redundancy using dynamic shifters An apparatus and method for controlling and providing off-pitch shifting circuitry for implementing column redundancy in a multiple-array memory is described in connection with an on-board cache memory integrated with a microprocessor. Depending upon the particular ... | 11/07/2006 |
