Famous Patents
Pong, the Atari creation that launched the computer game craze, came with these instructions: "Avoid missing ball for high score."
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7512017 | Integration of planar and tri-gate devices on the same substrate An apparatus including a first diffusion formed on a substrate, the first diffusion including a pair of channels, each of which separates a source from a drain; a second diffusion formed on the substrate, the second diffusion including a channel that separates a sou... | 03/31/2009 |
| 7440334 | Multi-transistor memory cells A memory cell having three transistors and a capacitor having metallic electrodes is described. Multiple memory cells may be arranged in a memory unit or array. Collective electrodes may be used in a space-saving embodiment of the capacitor. ... | 10/21/2008 |
| 7430137 | Non-volatile memory cells in a field programmable gate array A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel... | 09/30/2008 |
| 7420858 | Methods and apparatus for read/write control and bit selection with false read suppression in an SRAM Methods and apparatus are provided for read/write control and bit selection with false read suppression in an SRAM. According to one aspect of the invention, a bit select circuit is provided for an SRAM. The disclosed bit select circuit includes one or more transist... | 09/02/2008 |
| 7403426 | Memory with dynamically adjustable supply In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed. ... | 07/22/2008 |
| 7369452 | Programmable cell A device having an OTP memory is disclosed. A program state of the OTP device is stored at a fuse that is connected in series between a first node and a latch. During a program mode, the first node is electrically connected to a program voltage. During a read mode, ... | 05/06/2008 |
| 7355906 | SRAM cell design to improve stability A novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) an... | 04/08/2008 |
| 7321507 | Reference cell scheme for MRAM An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines ... | 01/22/2008 |
| 7321504 | Static random access memory cell A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter h... | 01/22/2008 |
| 7319605 | Conductive structure for microelectronic devices and methods of fabricating such structures A conductive structure for gate lines and local interconnects in microelectronic devices. The conductive structure can be used in memory cells for SRAM devices or other types of products. The memory device cell can comprise a first conductive line, a second conducti... | 01/15/2008 |
| 7311385 | Micro-fluid ejecting device having embedded memory device A semiconductor substrate for a micro-fluid ejecting device. The semiconductor substrate includes a plurality of fluid ejection devices disposed on the substrate. A plurality of driver transistors are disposed on the substrate for driving the plurality of fluid ejec... | 12/25/2007 |
| 7307871 | SRAM cell design with high resistor CMOS gate structure for soft error rate improvement A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through ... | 12/11/2007 |
| 7281231 | Integrated circuit structure and a design method thereof The present invention discloses an integrated circuit structure and a design method thereof, in which a circuit passageway is arranged at each circuit element terminal in circuit design stage. The arranged circuit passageway does not only increase layout flexibility... | 10/09/2007 |
| 7239558 | Method of hot electron injection programming of a non-volatile memory (NVM) cell array in a single cycle A non-volatile memory (NVM) cell splits its basic functions, i.e. program, erase, read and control, among a four PMOS transistor structure, allowing independent optimization of each cell function. The cell structure also includes an embedded static random access mem... | 07/03/2007 |
| 7221582 | Method and system for controlling write current in magnetic memory Methods and apparatuses are disclosed for controlling the write current in magnetic memory. In some embodiments, the method includes: providing a current in a plurality of memory write lines (where the write lines may be magnetically coupled to at least one memory e... | 05/22/2007 |
| 7190608 | Sensing of resistance variable memory devices A resistance variable memory device such as e.g., a PCRAM memory device, with either a 4T (transistor) or 2T memory cell configuration and either a dual cell plate or word line configuration. The device includes additional circuitry configured to write or erase addr... | 03/13/2007 |
| 7190031 | Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor laye... | 03/13/2007 |
| 7184299 | Nonvolatile SRAM memory cell An SRAM memory cell includes first and second inverters (14, 16) interconnected between first and second data nodes. Each inverter is formed from complementary MOS transistors (18, 20, 18′, 20′) connected in series between a DC voltage supply sourc... | 02/27/2007 |
| 7180802 | Method of stress-testing an isolation gate in a dynamic random access memory The present invention includes a DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first ... | 02/20/2007 |
| 7173589 | Display device A digital image signal fed from the drain signal line is written into a retaining circuit through a pixel element selection TFT and a liquid crystal displays an image based on the digital image signal. In the retaining circuit, a threshold voltage of the first inver... | 02/06/2007 |
| 7161215 | Semiconductor memory device and method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor laye... | 01/09/2007 |
| 7151688 | Sensing of resistance variable memory devices A resistance variable memory device such as e.g., a PCRAM memory device, with either a 4T (transistor) or 2T memory cell configuration and either a dual cell plate or word line configuration. The device includes additional circuitry configured to write or erase addr... | 12/19/2006 |
| 7151696 | Integrated circuit memory devices having hierarchical bit line selection circuits therein Integrated circuit memory devices include a first column of memory cells electrically coupled to a first pair of bit lines and a bit line precharge and selection circuit. This bit line precharge and selection circuit includes at least one stacked arrangement of thin... | 12/19/2006 |
| 7099206 | High density bitline selection apparatus for semiconductor memory devices A bitline selection apparatus for a semiconductor memory device includes a first local bitline pair and a second local bitline pair selectively coupled to a global bitline pair, each of the first and second local bitline pairs including a true bitline and a compleme... | 08/29/2006 |
| 7095657 | Nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. I... | 08/22/2006 |
| 7061794 | Wordline-based source-biasing scheme for reducing memory cell leakage A source-biasing mechanism for leakage reduction in SRAM. In standby mode, wordlines are deselected and a source-biasing potential is provided to SRAM cells. In read mode, a selected wordline deactivates the source-biasing potential provided to the selected row of S... | 06/13/2006 |
| 7057941 | Three-state memory cell A memory cell with at least two detectable states among which is an unprogrammed state, comprising, in series between two terminals of application of a read voltage, at least one first branch comprising: a pre-read stage comprising, in parallel, two switchable resis... | 06/06/2006 |
| 7027326 | 3T1D memory cells using gated diodes and methods of use thereof A memory cell comprises: (1) a write switch, the first terminal of the write switch coupled to an at least one bitline, the control terminal of the write switch coupled to the first control line; (2) a two terminal semiconductor, the first terminal of the two termin... | 04/11/2006 |
| 7005695 | Integrated circuitry including a capacitor with an amorphous and a crystalline high K capacitor dielectric region The invention comprises integrated circuitry and to methods of forming capacitors. In one implementation, integrated circuitry includes a capacitor having a first capacitor electrode, a second capacitor electrode and a high K capacitor dielectric region received the... | 02/28/2006 |
| 7002874 | Dual word line mode for DRAMs An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a second operational mode where two or more memory cells are dedicated to... | 02/21/2006 |
| 6999351 | Computer systems, processes for turning a SRAM cell off, and processes for writing a SRAM cell and processes for reading data from a SRAM cell A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell al... | 02/14/2006 |
| 6999362 | Method of stress-testing an isolation gate in a dynamic random access memory The present invention includes a DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first ... | 02/14/2006 |
| 6980468 | High density MRAM using thermal writing A memory cell includes a magnetic cell junction having an antiferromagnetic layer within a portion of the cell junction that is adapted to characterize a logic state of a bit written to the junction. More specifically, a memory cell includes, an antiferromagnetic la... | 12/27/2005 |
| 6977860 | SRAM power reduction A SRAM uses a number of memory banks in a configuration that uses lower voltage swings on a differential internal data bus so that the internal data bus no longer uses single-ended VDD/VSS, HIGH-to-LOW, rail-to-rail voltage swing for a read mode of operation. This c... | 12/20/2005 |
| 6977837 | Semiconductor memory including static random access memory formed of FinFET A semiconductor memory is formed of first, second, third, fourth, fifth and sixth field effect transistors. The first and second transistors have a first line as gates, one ends of current paths of the first and second transistors are connected to a reference potent... | 12/20/2005 |
| 6920061 | Loadless NMOS four transistor dynamic dual Vt SRAM cell Loadless 4T SRAM cells, and methods for operating such SRAM cells, which can provide highly integrated semiconductor memory devices while providing increased performance with respect to data stability and increased I/O speed for data access operations. A loadless 4T... | 07/19/2005 |
| 6900503 | SRAM formed on SOI substrate An SRAM capable of reducing the overall area consumed by the circuit and capable of improving the mobility and operational characteristics of a PMOS transistor is provided. The SRAM is formed on an SOI substrate having first and second active areas. A first access N... | 05/31/2005 |
| 6891743 | Semiconductor memory device having a capacitive plate to reduce soft errors A CMOS-SRAM has a plurality of full CMOS type memory cells (1) and a capacity plate (2). The memory cells (1) are two-dimensionally arranged in the row direction and in the column direction. The capacity plate 2 adds an additional capacit... | 05/10/2005 |
| 6888740 | Two-transistor SRAM cells A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell al... | 05/03/2005 |
| 6881623 | Method of forming chalcogenide comprising devices, method of forming a programmable memory cell of memory circuitry, and a chalcogenide comprising device A chalcogenide material is formed to a first thickness over the first conductive electrode material. The chalcogenide material includes AxBy. A layer that includes a metal is formed to a second thickness over the chalcogenide material. The meta... | 04/19/2005 |
