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| Number | Title | Issue Date |
| 8107301 | Memory controller A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus... | 01/31/2012 |
| 8089816 | Memory erase methods and devices Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low voltage string select gate transistors by maintaining the string select gate transistors in a turned on state du... | 01/03/2012 |
| 8027202 | Method of programming a flash memory device using self boosting A method of programming a flash memory device controls a channel boosting level to ensure device properties. The flash memory device is programmed in an Incremental Step Pulse Program (ISPP) manner by applying a program voltage to a selected memory cell and a pass v... | 09/27/2011 |
| 8000153 | Enhanced erase for flash storage device A flash storage device includes flash storage units that are erased in response to a condition or command while allowing the flash storage device to be used subsequent to the erase. A flash controller interface receives a command for erasing the flash storage device... | 08/16/2011 |
| 7969791 | Memory configuration of a composite memory device The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control ... | 06/28/2011 |
| 7965563 | Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of... | 06/21/2011 |
| 7929354 | Verified purge for flash storage device A flash storage device includes flash storage units that are purged in response to a condition or command wherein, during or subsequent to the purge, the purge is verified. A flash controller interface receives a command for purging the flash storage device and prov... | 04/19/2011 |
| 7916553 | Memory system and method having volatile and non-volatile memory devices at same hierarchical level A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dyn... | 03/29/2011 |
| 7903474 | Redundant purge for flash storage device A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage dev... | 03/08/2011 |
| 7881124 | Method for block writing in a memory A method is provided for block writing in an electrically programmable non-volatile memory, in which a block to be written in the memory includes at least one word. The method includes determining a word write time by dividing a fixed block write time by the number ... | 02/01/2011 |
| 7876623 | Program method with optimized voltage level for flash memory A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the percentage of the data bits that failed programming verification during the previous programming cycle and we... | 01/25/2011 |
| 7872922 | Memory system and method of writing into nonvolatile semiconductor memory A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first t... | 01/18/2011 |
| 7835194 | Erase operation in a flash memory device A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the threshold voltages indicate erased cells. A target cell is programmed to a first threshold voltage and verif... | 11/16/2010 |
| 7791955 | Method of erasing a block of memory cells A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a commo... | 09/07/2010 |
| 7742344 | Method and apparatus for improving storage performance using a background erase Disclosed are an apparatus, method, and computer readable medium configured for performing a background erase in a memory device. Included is the act of receiving at least one erase command and at least one erasable block address for the memory device. Also included... | 06/22/2010 |
| 7738304 | Multiple use memory chip A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits. ... | 06/15/2010 |
| 7733706 | Flash memory device and erase method thereof A flash memory device and an erase method thereof are included. The erase method includes performing an erase operation of a memory cell block including a plurality of pages, performing an erase verify operation and storing unerased page information about a page inc... | 06/08/2010 |
| 7710788 | Flash memory device and method of testing a flash memory device A flash memory device includes a flash fuse cell array, a trim code processing unit, a flash memory array, and a regulator. The fuse cell array, which includes multiple nonvolatile fuse cells, is configured to store a first trim code. The trim code processor is conf... | 05/04/2010 |
| 7692973 | Semiconductor device A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, source and drain regions, a floating gate, and a control g... | 04/06/2010 |
| 7684256 | Flash memory device and program method A method for programming a flash memory device includes selecting bit lines connected to a plurality of memory strings and selecting a word line. A lower bit is programmed into the memory cells connected to the selected word line and programming a upper bit into the... | 03/23/2010 |
| 7675788 | Electronic non-volatile memory device having a cNAND structure and being monolithically integrated on semiconductor A non-volatile electronic memory device may be monolithically integrated on a semiconductor and be of the Flash EEPROM type having a NAND architecture and including at least one memory matrix organized in rows and columns of memory cells. Advantageously, the matrix ... | 03/09/2010 |
| 7672172 | Memory configuration of a composite memory device The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control ... | 03/02/2010 |
| 7663934 | Program method with optimized voltage level for flash memory A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the percentage of the data bits that failed programming verification during the previous programming cycle and we... | 02/16/2010 |
| 7609562 | Configurable device ID in non-volatile memory Various embodiments of the invention may use one or more programmable non-volatile registers in each memory device to provide a separate device address for that device. These registers may be programmed at various points in the manufacturing and distribution cycle, ... | 10/27/2009 |
| 7609561 | Disabling faulty flash memory dies Articles and associated methods and systems relate to disabling defective flash memory dies in a device containing multiple flash memory dies. Packages containing multiple flash memory dies may be labeled to indicate a flash memory data storage capacity based on the... | 10/27/2009 |
| 7593269 | Differential flash memory programming technique The invention relates flash memory programming techniques. An object of the invention is to provide a flash memory programming technique avoiding problems of the known state of the art and in particular, saving a significant amount of time during the development and... | 09/22/2009 |
| RE40917 | Memory configuration of a composite memory device The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control ... | 09/15/2009 |
| 7583540 | Flash memory device and method of programming the same A flash memory device and a method of programming the same are disclosed. The flash memory device includes an array of memory cells intersected by a plurality of bit lines and a plurality of word lines. A page buffer circuit includes a plurality of latches coupled t... | 09/01/2009 |
| 7564721 | Method and apparatus for improving storage performance using a background erase Disclosed are an apparatus, method, and computer readable medium configured for performing a background erase in a memory device. Included is the act of receiving at least one erase command and at least one erasable block address for the memory device. Also included... | 07/21/2009 |
| 7564722 | Memory system and method having volatile and non-volatile memory devices at same hierarchical level A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dyn... | 07/21/2009 |
| 7558121 | Flash memory device and smart card including the same A flash memory device includes an array having memory cells arranged in rows and columns. A high voltage generator is configured to supply a high voltage to the array during a programming operation. Write buffers corresponding to selected memory cells drive the sele... | 07/07/2009 |
| 7558122 | Flash memory device and method of erasing flash memory device A flash memory device and a method of erasing memory cells in a flash memory device are provided. A first post program operation is performed on erased memory cells having a threshold voltage lower than a first program verify voltage. A second post program operation... | 07/07/2009 |
| 7545682 | Erase block data splitting A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memor... | 06/09/2009 |
| 7542354 | Reprogrammable nonvolatile memory devices and methods A nonvolatile memory device includes a command decoder configured to generate a read/write flag signal in response to a read/write command and to generate a reprogram flag signal in response to a reprogram command, and a read/write circuit configured to control read... | 06/02/2009 |
| 7525848 | Method for erasing and changing data of floating gate flash memory A method for erasing data stored in the memory cells of the floating gate flash memory is included. The method allows a plurality of sectors to be disposed in a same P well. The method includes erasing data stored in a first set of memory cells according to a contro... | 04/28/2009 |
| 7505329 | Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of... | 03/17/2009 |
| 7499339 | High-performance flash memory data transfer A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously wi... | 03/03/2009 |
| 7489562 | Multiple use memory chip A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits. ... | 02/10/2009 |
| 7483312 | Memory configuration of a composite memory device The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control ... | 01/27/2009 |
| 7480187 | Nonvolatile semiconductor memory with low-loading bit line architecture and method of programming the same A NAND flash memory device includes an array of NAND flash memory cells; a plurality of word lines connected to the NAND flash memory cells; and a plurality of bit lines connected to the NAND flash memory cells. Each bit line includes a first bit line portion, a sec... | 01/20/2009 |
