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| Number | Title | Issue Date |
| 8189399 | EEPROM having single gate structure and method of operating the same An electrically erasable programmable read-only memory (EEPROM) includes an access transistor having a floating gate and source/drain regions formed at opposite sides of the floating gate in a first well, a first well tap formed in the first well, a control gate loc... | 05/29/2012 |
| 8174905 | Programming orders for reducing distortion in arrays of multi-level analog memory cells A method for data storage includes predefining an order of programming a plurality of analog memory cells that are arranged in rows. The order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are pro... | 05/08/2012 |
| 8149631 | Non-volatile semiconductor storage device For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase... | 04/03/2012 |
| 8144522 | Erasing flash memory using adaptive drain and/or gate bias A hot hole erase operation as described herein can be utilized for a flash memory device having an array of memory cells. The erase operation employs an adaptive erase bias voltage scheme where the drain bias voltage (and/or the gate bias voltage) is dynamically adj... | 03/27/2012 |
| 8139421 | Erase degradation reduction in non-volatile memory Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step. The intermediate erase step is comprised of an erase pulse voltage, ... | 03/20/2012 |
| 8130555 | Nonvolatile semiconductor storage device and method of erase verifying the same A nonvolatile semiconductor storage device including a NAND cell unit having a first and a second select gate transistor, a plurality of memory cell transistors series connected between the first and second select gate transistors that are coupled to corresponding w... | 03/06/2012 |
| 8125835 | Memory architecture having two independently controlled voltage pumps In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array du... | 02/28/2012 |
| 8125836 | Verifying an erase threshold in a memory device In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, th... | 02/28/2012 |
| 8116142 | Method and circuit for erasing a non-volatile memory cell The present invention is a method, circuit and system for erasing a non-volatile memory cell. A shunting element (e.g. transistor) may be introduced and/or activated between bit-lines to which one or more NVM cells being erased are connected. The shunting element ma... | 02/14/2012 |
| 8116143 | Method of erasing memory cell An embodiment of a method of erasing a target memory cell includes grounding a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed... | 02/14/2012 |
| 8102719 | Semiconductor memory device capable of compensating variation with time of program voltage A voltage generating circuit generates, at a time of write, a first voltage which is higher than a program voltage, and generates an erase voltage at a time of erase. A first transistor has a current path and a gate, and the first voltage generated by the voltage ge... | 01/24/2012 |
| 8098530 | Systems and methods for erasing a memory Methods of erasing a memory, methods of operating a memory, memory devices, and systems. In one such method, an erase block is erased to an intermediate erase voltage before it is erased to a final erase voltage, such as to tighten an erase distribution. Faster eras... | 01/17/2012 |
| 8081521 | Two bits per cell non-volatile memory architecture A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high val... | 12/20/2011 |
| 8081519 | Adaptive erase and soft programming for memory An erase sequence of a non-volatile storage device includes an erase operation followed by a soft programming operation. The erase operation applies one or more erase pulses to the storage elements, e.g., via a substrate, until an erase verify level is satisfied. Th... | 12/20/2011 |
| 8077525 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device includes: a memory cell array configured to have a plurality of blocks arranged thereon, each of the blocks being configured by an assembly of NAND cell units, each of the NAND cell units including a plurality of nonvolatile... | 12/13/2011 |
| 8064267 | Erase voltage reduction in a non-volatile memory device In erasing a memory block of memory cells, a semiconductor tub that contains a memory block to be erased can be biased with a high, positive voltage. The control gates of the memory cells that make up the memory block can be biased with a negative voltage. An erase ... | 11/22/2011 |
| 8059474 | Reducing read failure in a memory device Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a p... | 11/15/2011 |
| 8050106 | Fast writing non-volatile memory with main and auxiliary memory areas A method writes data in a non-volatile memory comprising memory cells that are erased before being written. The method comprises the steps of providing a main non-volatile memory area comprising target pages, providing an auxiliary non-volatile memory area comprisin... | 11/01/2011 |
| 8050107 | Non-volatile memory including an auxiliary memory area with rotating sectors A method writes data in a non-volatile memory. The method provides, in the memory, a non-volatile main memory area comprising target pages, a non-volatile auxiliary memory area comprising auxiliary pages, and, in the auxiliary memory area: a current sector comprisin... | 11/01/2011 |
| 8036044 | Dynamically adjustable erase and program levels for non-volatile memory Degradation of non-volatile storage elements is reduced by adaptively adjusting erase-verify levels and program-verify levels. The number of erase pulses, or the highest erase pulse amplitude, needed to complete an erase operation is determined. When the number, or ... | 10/11/2011 |
| 8023336 | Erase completion recognition Embodiments include but are not limited to apparatuses and systems including a main memory array, at least one erase status memory cell associated with the main memory array and configured to store a value indicative of an erase completion status of the main memory ... | 09/20/2011 |
| 8018781 | Method of operating nonvolatile memory device Provided is a method of operating a nonvolatile memory device to perform an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and a DC perturbation pulse to the nonvolatile memory device to perform the erase operat... | 09/13/2011 |
| 8018782 | Non-volatile memory devices and methods of erasing non-volatile memory devices In one embodiment, an erase method for a memory including a memory array having at least first and second programmable transistors connected in series, includes restricting flow of electrons from the first programmable transistor into the second programmable transis... | 09/13/2011 |
| 8014209 | Programming and selectively erasing non-volatile storage A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements that were supposed to remain erased, without intentionally erasing progr... | 09/06/2011 |
| 8014210 | Non-volatile memory control circuit An efficient erasure is performed. The voltage of a source line SL is manipulated in units of a sector providing a plurality of memory cells. An erase command is received for the desired memory cells to be erased in a plurality of word line WL units arranged within ... | 09/06/2011 |
| 8009483 | Nonvolatile memory cell and data latch incorporating nonvolatile memory cell A nonvolatile memory cell includes: a first NMOS transistor having a floating gate; a second NMOS transistor and a third NMOS transistor connected to a drain side and a source side of the first NMOS transistor; and a first PMOS transistor and a second PMOS transisto... | 08/30/2011 |
| 8004905 | Nonvolatile memory system, semiconductor memory and writing method A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing oper... | 08/23/2011 |
| 8004906 | Nonvolatile memory device and method of operating and fabricating the same Provided is a method of reliably operating a highly integratable nonvolatile memory device. The nonvolatile memory device may include a string selection transistor, a plurality of memory transistors, and a ground selection transistor between a bit line and a common ... | 08/23/2011 |
| 7995401 | Non-volatile semiconductor memory with page erase In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordl... | 08/09/2011 |
| 7990775 | Methods of operating memory devices including different sets of logical erase blocks Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second set of logical erase blocks. The logical erase blocks of the first set of logical erase blocks each have a f... | 08/02/2011 |
| 7990774 | Communication device and method for erasing data from a communication device A communication device and method for erasing data include setting erasing parameters and initializing the erasing parameters, erasing data in a target data block of the flash memory once, and calculate a current erasing count of the erased block, setting a first bi... | 08/02/2011 |
| 7986564 | High second bit operation window method for virtual ground array with two-bit memory cells A non-volatile VG memory array employing memory semiconductor cells capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in associating with at least one electrical insulating layer, such as ... | 07/26/2011 |
| 7986565 | Method of erasing data in flash memory device A method of erasing data in a flash memory device, including erasing data in at least one flash memory cell using a first erase voltage; detecting whether the at least one flash memory cell has a threshold voltage less than a first voltage; programming the at least ... | 07/26/2011 |
| 7983093 | Non-volatile memory cell with BTBT programming A Non-Volatile Memory (NVM) cell and programming method in which the cell can denote at least two logic levels (e.g., 0 and 1) and includes a read-transistor with a floating gate and a Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the re... | 07/19/2011 |
| 7978533 | NAND flash memory with a programming voltage held dynamically in a NAND chain channel region Operating voltages to a group of memory cells in an array are supplied via access lines such as word lines and bit lines. The capacitance of associated nodes of the memory cells can latch some of these voltages. Memory operation can continue using the latched voltag... | 07/12/2011 |
| 7978532 | Erase method of flash memory device Erase and program methods of a flash memory device including MLCs for increasing the program speed. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ... | 07/12/2011 |
| 7974136 | Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channe... | 07/05/2011 |
| 7969790 | Method of erasing an NVM cell that utilizes a gated diode A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining ... | 06/28/2011 |
| 7961525 | Method for deleting data from NAND type nonvolatile memory To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In t... | 06/14/2011 |
| 7952938 | Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The o... | 05/31/2011 |
