Class 365/185.27 - Substrate bias

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter under 185.18 wherein the floating gate device
No. of patents: 519
Last issue date: 05/01/2012

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Number	Title	Issue Date
8169834	Sense amplifier used in electrically erasable programmable read-only memory and the implementing method thereof A sense amplifier and method of implementing includes a reference current generation circuit, which is used for providing a reference current with a settable temperature coefficient for a main circuit of the sense amplifier; the main circuit is used for comparing th...	05/01/2012
8149629	Semiconductor storage device adapted to prevent erroneous writing to non-selected memory cells A memory cell array has a number of memory cells which are connected to word lines and bit lines and are arranged in a matrix form, each of the memory cells storing one of n levels (n is a natural number of 2 or more). A control circuit controls the potentials on th...	04/03/2012
8031532	Methods of operating embedded flash memory devices Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to is...	10/04/2011
8018780	Temperature dependent back-bias for a memory array The present invention provides a thermostatic bias controller for use with a memory array. The thermostatic bias controller includes a temperature sensing circuit configured to sense a temperature associated with the memory array. The thermostatic bias controller al...	09/13/2011
7990773	Sub volt flash memory system Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply vol...	08/02/2011
7986563	NAND flash memory programming A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is...	07/26/2011
7903472	Operating method of non-volatile memory An operating method of a non-volatile memory adapted for a non-volatile memory disposed on an SOI substrate including a first conductive type silicon body layer is provided. The non-volatile memory includes a gate, a charge storage structure, a second conductive typ...	03/08/2011
7778086	Erase operation control sequencing apparatus, systems, and methods Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled t...	08/17/2010
7710786	NAND flash memory programming A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is...	05/04/2010
7688642	Non-volatile memory device and method for programming/erasing the same Provided are a SONGS type nonvolatile or flash memory device and related programming/erasing methods. The device has a deep well region of a first conductive type that isolates a well region of a second conductive type from a substrate to enhance programming and era...	03/30/2010
7675785	Semiconductor storage device There is provided a semiconductor storage device including a substrate area, a first and a second isolation area, a first well area where the first transistor is placed, a second well area where the second transistor to output a first voltage to bring the first tran...	03/09/2010
7672170	Flash memory device and program method thereof A method for programming a flash memory device with a plurality of memory cells. A selected memory cell is programmed under a condition where a bulk area is biased with a high voltage. A program pass/fail of the memory cell is verified with the high voltage applied ...	03/02/2010
7649786	Non-volatile memory architecture and method, in particular of the EEPROM type A memory architecture includes at least one matrix of memory cells of the EEPROM type organized in rows or word lines and columns or bit lines. Each memory cell includes a floating gate cell transistor and a selection transistor and is connected to a source line sha...	01/19/2010
7583539	Non-volatile storage with bias for temperature compensation A non-volatile storage system in which a body bias is applied to a non-volatile storage system to compensate for temperature-dependent variations in threshold voltage, sub-threshold slope, depletion layer width and/or 1/f noise. A desired bias level is set based on ...	09/01/2009
7567484	Method of preventing dielectric breakdown of semiconductor device and semiconductor device preventing dielectric breakdown A semiconductor device that prevents a build-up of electrostatic charge in a dummy pad is provided. The semiconductor device may contain an internal circuit formed on a semiconductor substrate and the dummy pad which is not electrically connected to the internal cir...	07/28/2009
7554853	Non-volatile storage with bias based on selective word line A non-volatile storage system in which a body bias is applied to compensate for performance variations which are based on the position of a selected word line which is associated with non-volatile storage elements undergoing program, read or verify operations. In on...	06/30/2009
7480185	Ballistic injection NROM flash memory A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The nitride ...	01/20/2009
7468920	Applying adaptive body bias to non-volatile storage Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bia...	12/23/2008
7468919	Biasing non-volatile storage based on selected word line A body bias is applied to a non-volatile storage system to compensate for performance variations which are based on the position of a selected word line which is associated with non-volatile storage elements undergoing program, read or verify operations. In one appr...	12/23/2008
7443722	Semiconductor device and driving method therefor A semiconductor device includes a bulk semiconductor substrate, a plurality of storage elements, a bit line, a first voltage being applied to the first region side of the thyristor, and a voltage lower than the first voltage being applied to a word line. The plurali...	10/28/2008
7443736	Substrate electron injection techniques for programming non-volatile charge storage memory cells and for controlling program disturb A programming technique for a flash memory causes electrons to be injected from the substrate into charge storage elements of the memory cells. The source and drain regions of memory cells along a common word line or other common control gate line being programmed b...	10/28/2008
7436716	Nonvolatile memory A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direc...	10/14/2008
7433234	Floating-body cell (FBC) semiconductor storage device having a buried electrode serving as gate electrode, and a surface electrode serving as plate electrode A semiconductor storage device including a memory cell. In the memory cell a buried electrode is formed on a semiconductor substrate. A semiconductor layer is formed on the buried electrode via a buried insulating film. A surface electrode is formed on the semicondu...	10/07/2008
7433242	Semiconductor memory device and driving method of the same A semiconductor memory device includes a semiconductor substrate including a semiconductor layer on a first insulation film; a memory cell including a source and a drain formed in the semiconductor layer, and a floating body region provided between the source and th...	10/07/2008
7430138	Erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells Voltage conditions applied to the memory cells of a non-volatile memory system are changed during erase operations in order to equalize the erase behavior of the select memory cells with other memory cells of the system that are being concurrently erased. The change...	09/30/2008
7428173	Low power NROM memory devices A buried bipolar junction is provided in a charge trapping transistor memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and inje...	09/23/2008
7420852	Non-volatile memory device providing controlled bulk voltage during programming operations Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device comprises a plurality of memory cells that are programmed by supplying first and second program voltages thereto. In cases where the second program voltage...	09/02/2008
7420842	Method of programming a three-terminal non-volatile memory element using source-drain bias A storage transistor is programmed as a non-volatile memory element by biasing the source and drain while a programming voltage is applied to the gate. The substrate is held at a different potential than the source/drain to insure that the greatest difference in vol...	09/02/2008
7420840	Semiconductor device that is advantageous in operational environment at high temperatures A semiconductor device comprises an N-type insulated-gate field-effect transistor including a first insulating layer that is provided along side walls of a gate electrode, has a negative thermal expansion coefficient, and applies a tensile stress to a channel region...	09/02/2008
7420853	Semiconductor storage device and semiconductor storage device driving method A semiconductor storage device comprises a semiconductor layer; a plurality of memory cells formed on the semiconductor layer, data writing, erasing or reading with respect to each of the memory cells being possible based on a voltage applied to a control electrode ...	09/02/2008
7417897	Method for reading a single-poly single-transistor non-volatile memory cell A method for operating a single-poly, single-transistor (1-T) non-volatile memory (NVM) cell. The NVM cell includes a gate on a P substrate, a gate dielectric layer, an N drain region and an N source region. N channel is defined between the N drain region and N sour...	08/26/2008
7411834	Nonvolatile semiconductor memory device A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is ...	08/12/2008
7411835	Discharge circuit for a capacitive load A circuit arrangement for the defined discharge of a capacitive load includes a first connecting terminal for connection of the load, a second connecting terminal for application of a predetermined potential, and a third connecting terminal for application of a disc...	08/12/2008
7408798	3-dimensional integrated circuit architecture, structure and method for fabrication thereof An integrated circuit design, structure and method for fabrication Thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently opt...	08/05/2008
7400530	Semiconductor memory A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gate...	07/15/2008
7397706	Methods of erasing flash memory devices by applying wordline bias voltages having multiple levels and related flash memory devices Methods of erasing data in a flash memory device are provided in which a plurality of wordline bias voltages are generated that include wordline bias voltages having at least two different levels, erasing data by applying the different wordline bias voltages to resp...	07/08/2008
7397699	Channel discharging after erasing flash memory devices A post-erase channel clearing procedure for double well, floating gate, non-volatile memory cells. The channel is cleared of charged particles coming from the floating gate after an erase operation in two steps. In the first step the charged particles are pushed int...	07/08/2008
7395466	Method and apparatus to adjust voltage for storage location reliability According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storag...	07/01/2008
7394708	Adjustable global tap voltage to improve memory cell yield A system that increases device yield by correcting improper operation of the device's memory cells due to process variations is disclosed. The device includes an array of memory cells and an adjustable bias voltage circuit, and is coupled to a test circuit that gene...	07/01/2008
7391653	Twin insulator charge storage device operation and its fabrication method The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the pro...	06/24/2008

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Class 365/185.27 - Substrate bias