Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
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| Number | Title | Issue Date |
| 8107300 | Non-volatile semiconductor memory device comprising capacitive coupling program inhibit circuitry According to an one aspect of the present invention, it is provided a non-volatile semiconductor memory device comprising: a first N type well; a plurality of P type non-volatile memory cells arranged in matrix and formed in the N type well; a plurality of sub-bit l... | 01/31/2012 |
| 8098529 | Memory device having buried boosting plate and methods of operating the same Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coup... | 01/17/2012 |
| 8089815 | Programming memory with bit line floating to reduce channel-to-floating gate coupling During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. Programming speed can be adjusted by grounding the bit line of a selected storage elem... | 01/03/2012 |
| 8050105 | FLOTOX-type EEPROM In designing a FLOTOX EEPROM of a dual cell type, a consideration should be given to the layout of cells for microminiaturization of the FLOTOX EEPROM. The FLOTOX EEPROM of the dual cell type includes two paired floating gates (25a, 25b),... | 11/01/2011 |
| 7990772 | Memory device having improved programming operation Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation. ... | 08/02/2011 |
| 7983092 | Nonvolatile memory apparatus and method of using thin film transistor as nonvolatile memory The present invention relates to a nonvolatile memory apparatus and a method of using a thin film transistor (TFT) as a nonvolatile memory by storing carriers in a body of the TFT, which operates a general TFT as a memory cell of a nonvolatile memory by manipulating... | 07/19/2011 |
| 7936611 | Memory device and method of operating and fabricating the same A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, ... | 05/03/2011 |
| 7916550 | Method and apparatus for operating nonvolatile memory with floating voltage at one of the source and drain regions Methods and apparatuses are discussed which operate a nonvolatile memory cell or at least one cell in an array of such cells, such that a drain region or a source region is floating while adding charge to the charge storage structure. ... | 03/29/2011 |
| 7855920 | Semiconductor memory device having a floating storage bulk region capable of holding/emitting excessive majority carriers A semiconductor memory device includes: a semiconductor layer formed on an insulating layer; a plurality of transistors formed on the semiconductor layer and arranged in a matrix form, each of the transistors having a gate electrode, a source region and a drain regi... | 12/21/2010 |
| 7843740 | Method for driving a nonvolatile semiconductor memory device A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device includes a semiconductor layer having a channel, a first insulating film provided on the channel, a floating electrode provided on the first insul... | 11/30/2010 |
| 7830722 | Floating body memory cell system and method of manufacture A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may incl... | 11/09/2010 |
| 7773428 | Nonvolatile semiconductor memory having suitable crystal orientation An NMOS transistor type nonvolatile semiconductor memory has first and second N-type diffusion layers formed in a P-type silicon layer as a source and a drain; a gate electrode formed on a channel region with an insulating film interposed therebetween, the channel r... | 08/10/2010 |
| 7764549 | Floating body memory cell system and method of manufacture A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may incl... | 07/27/2010 |
| 7710785 | Semiconductor memory device having a floating storage bulk region capable of holding/emitting excessive majority carriers A semiconductor memory device includes: a semiconductor layer formed on an insulating layer; a plurality of transistors formed on the semiconductor layer and arranged in a matrix form, each of the transistors having a gate electrode, a source region and a drain regi... | 05/04/2010 |
| 7697344 | Memory device and method of operating and fabricating the same A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, ... | 04/13/2010 |
| 7692972 | Split gate memory cell for programmable circuit device A split-gate memory cell, includes an n-channel split-gate non-volatile memory transistor having a source, a drain, a select gate over a thin oxide, and a control gate over a non-volatile gate material and separated from the select gate by a gap. A p-channel pull-up... | 04/06/2010 |
| 7660165 | Memory device and semiconductor device A memory device has a pair of conductive layers and an organic compound having a liquid crystal property that is interposed between the pair of conductive layers. Data is recorded in the memory device by applying a first voltage to the pair of conductive layers and ... | 02/09/2010 |
| 7633811 | Non-volatile memory embedded in a conventional logic process and methods for operating same A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the sourc... | 12/15/2009 |
| 7633810 | Non-volatile memory embedded in a conventional logic process and methods for operating same A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the sourc... | 12/15/2009 |
| 7583538 | Semiconductor memory and read method of the same A semiconductor memory including a memory cell which is a MOSFET formed on an SOI substrate. The memory cell has a gate electrode connected to a word line, a drain region connected to a bit line, and a grounded source region. An operation of reading out data written... | 09/01/2009 |
| 7525846 | Memory device A memory device includes a memory cell having a capacitor for accumulating electric charges in accordance with the logic of data, a bit line connected to the memory cell, a charge transfer circuit for transferring the electric charges in the bit line to an output no... | 04/28/2009 |
| 7515478 | CMOS logic compatible non-volatile memory cell structure, operation, and array configuration The present invention is to provide a logic based single-poly non-volatile memory cell which is compatible with the CMOS process, uses lower voltages for operating, and is more reliable in program, read, or erase operation. A non-volatile memory cell in accordance w... | 04/07/2009 |
| 7512012 | Non-volatile memory and manufacturing method and operating method thereof and circuit system including the non-volatile memory The memory cell includes a first unit, a semiconductor layer, a second unit, and a doped region. The first unit includes a first gate, a first charge trapping layer, and a second charge trapping layer. The first and the second charge trapping layer are respectively ... | 03/31/2009 |
| 7483310 | System and method for providing high endurance low cost CMOS compatible EEPROM devices A system and method are disclosed for providing EEPROM devices that combine the high endurance features of complex and expensive EEPROM devices and the low manufacturing costs of CMOS compatible EEPROM devices. A memory cell of the invention comprises a control capa... | 01/27/2009 |
| 7450431 | PMOS three-terminal non-volatile memory element and method of programming A PMOS transistor is programmed as a non-volatile memory element by operating the PMOS transistor in accumulation mode. This facilitates merging the source and drain regions to form a low-resistance path because most heating occurs on the channel side of the gate di... | 11/11/2008 |
| 7443736 | Substrate electron injection techniques for programming non-volatile charge storage memory cells and for controlling program disturb A programming technique for a flash memory causes electrons to be injected from the substrate into charge storage elements of the memory cells. The source and drain regions of memory cells along a common word line or other common control gate line being programmed b... | 10/28/2008 |
| 7443729 | System that compensates for coupling based on sensing a neighbor using coupling Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing ele... | 10/28/2008 |
| 7440311 | Single-poly non-volatile memory cell A non-volatile memory cell includes a floating gate transistor having a floating gate coupled to a metal layer capacitor defined in one or more metal layers. Within each metal layer, the metal layer capacitor includes a first plate coupled to the floating gate and a... | 10/21/2008 |
| 7440329 | Floating body cell (FBC) memory device with a sense amplifier for refreshing dummy cells This disclosure concerns a semiconductor memory including memory cells; a first dummy cell and a second dummy cell generating a reference potential and storing first data and second data of mutually opposite polarities, respectively; word lines; a first and a second... | 10/21/2008 |
| 7436707 | Flash memory cell structure and operating method thereof A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and ... | 10/14/2008 |
| 7436706 | Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing same There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, circuitry and techniques for reading, writing and/or operating a semiconductor memory cells of a memory cell array, including electrically floating b... | 10/14/2008 |
| 7433234 | Floating-body cell (FBC) semiconductor storage device having a buried electrode serving as gate electrode, and a surface electrode serving as plate electrode A semiconductor storage device including a memory cell. In the memory cell a buried electrode is formed on a semiconductor substrate. A semiconductor layer is formed on the buried electrode via a buried insulating film. A surface electrode is formed on the semicondu... | 10/07/2008 |
| 7428167 | Semiconductor integrated circuit and nonvolatile memory element A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plu... | 09/23/2008 |
| 7428165 | Self-boosting method with suppression of high lateral electric fields In an improved EASB programming scheme for a flash device (e.g. a NAND flash device), the number of word lines separating a selected word line (to which a program voltage is applied) and an isolation word line (to which an isolation voltage is applied) is adjusted a... | 09/23/2008 |
| 7423906 | Integrated circuit having a memory cell A memory cell having a programmable solid state electrolyte layer, a writing line and a controllable switch that is arranged between the solid state electrolyte layer and the writing line. The controllable switch has a control input that is connected with a selectin... | 09/09/2008 |
| 7420840 | Semiconductor device that is advantageous in operational environment at high temperatures A semiconductor device comprises an N-type insulated-gate field-effect transistor including a first insulating layer that is provided along side walls of a gate electrode, has a negative thermal expansion coefficient, and applies a tensile stress to a channel region... | 09/02/2008 |
| 7420842 | Method of programming a three-terminal non-volatile memory element using source-drain bias A storage transistor is programmed as a non-volatile memory element by biasing the source and drain while a programming voltage is applied to the gate. The substrate is held at a different potential than the source/drain to insure that the greatest difference in vol... | 09/02/2008 |
| 7417890 | Semiconductor memory device A semiconductor memory device is disclosed, which includes a first SRAM cell which includes cross-connected first and second inverters having first and second nodes, a first transistor connected between a first bit line and the first node and having a gate connected... | 08/26/2008 |
| 7417893 | Integrated DRAM-NVRAM multi-level memory An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a... | 08/26/2008 |
| 7405971 | Semiconductor device A semiconductor integrated circuit includes non-volatile memory elements (PM1, PM2), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshol... | 07/29/2008 |
