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| Number | Title | Issue Date |
| 7515476 | Non-volatile memory device and data read method and program verify method of non-volatile memory device A non-volatile memory device includes an even bit line and an odd bit line, a first register, a second register, a first precharge unit, a second precharge unit and a bit line select unit. The even bit line and the odd bit line are connected to a memory cell array. ... | 04/07/2009 |
| 7512011 | Method of reading data in a non-volatile memory device A method of reading data in a non-volatile memory device includes providing a plurality of blocks and a plurality of bit lines, each block having a plurality of memory cells, each block coupled to at least one bit line. First and second bit lines are discharged to b... | 03/31/2009 |
| 7505327 | Method of controlling a semiconductor device by a comparison of times for discharge of bit lines connected to different memory cell arrays A semiconductor memory device includes a memory cell array, first bit lines, second bit lines, a first precharge circuit, a sense amplifier, and a read control circuit. The memory cell array has a first cell array including first memory cells arranged in a matrix an... | 03/17/2009 |
| 7499334 | Method and apparatus for discharging a memory cell in a memory device after an erase operation A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a fir... | 03/03/2009 |
| 7489559 | Recursive device for switching over a high potential greater than a nominal potential of a technology in which the device is made and related system and method An embodiment of the invention pertains to an nth order selector switch device comprising: a first arm comprising n transistors series-connected between a first input to which a 0-ranking potential is applied, and an output; and a second arm comprising n ... | 02/10/2009 |
| 7486566 | Methods, apparatus, and systems for flash memory bit line charging Various embodiments include a circuit to receive data information, a memory array including memory cells coupled to a bit line, and control circuitry to charge the bit line while the data information is received at the circuit. The control circuitry may program the ... | 02/03/2009 |
| 7471569 | Memory having parity error correction A memory includes a sense amplifier segment and a plurality of word lines including a first transfer word line and a second transfer word line complementary to the first transfer word line. The memory includes a plurality of bit lines coupled to the sense amplifier ... | 12/30/2008 |
| 7468918 | Systems for programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and bo... | 12/23/2008 |
| 7463531 | Systems for programming non-volatile memory with reduced program disturb by using different pre-charge enable voltages Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and bo... | 12/09/2008 |
| 7460409 | Electrically writable nonvolatile memory A nonvolatile memory includes a memory cell array in which a plurality of memory cells are connected to a plurality of wordlines and a plurality of bitlines respectively intersecting at a right angle with the plurality of wordlines; a selector for selecting one of t... | 12/02/2008 |
| 7450430 | Programming non-volatile memory with reduced program disturb by using different pre-charge enable voltages Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and bo... | 11/11/2008 |
| 7443728 | NAND flash memory device and method of programming same Disclosed is a NAND flash memory device comprising a memory cell array connected to a page buffer via a plurality of bitlines. The page buffer stores input data to be programmed in the memory cell array. The memory cell array is programmed by establishing bitline vo... | 10/28/2008 |
| 7440329 | Floating body cell (FBC) memory device with a sense amplifier for refreshing dummy cells This disclosure concerns a semiconductor memory including memory cells; a first dummy cell and a second dummy cell generating a reference potential and storing first data and second data of mutually opposite polarities, respectively; word lines; a first and a second... | 10/21/2008 |
| 7440328 | Operation methods for a non-volatile memory cell in an array A method of reducing gate disturb in a charge-trapping layer memory cell by applying different Vpass voltages to different sides of a selected wordline. A higher Vpass voltage is used to pass higher source/drain voltage and a lower Vpass voltage is used to pass a lo... | 10/21/2008 |
| 7440318 | Reducing read disturb for non-volatile storage A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents... | 10/21/2008 |
| 7436691 | Semiconductor storage device, operation method of the same and test method of the same A semiconductor storage device includes a bit line; a word line; a plate line; a ferroelectric capacitor having a ferroelectric substance between electrodes, one of the electrodes being connected to the plate line, the ferroelectric capacitor being capable of storin... | 10/14/2008 |
| 7433230 | Nonvolatile semiconductor memory device having assist gate In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit li... | 10/07/2008 |
| 7433241 | Programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and bo... | 10/07/2008 |
| 7420850 | Method for controlling current during programming of memory cells Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to isolate the memory cells from potentially damaging electrical energy that can be imposed during a precharge phase that precede... | 09/02/2008 |
| 7420851 | Memory device for controlling current during programming of memory cells Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to isolate the memory cells from potentially damaging electrical energy that can be imposed during a precharge phase that precede... | 09/02/2008 |
| 7417900 | Method and system for refreshing a memory device during reading thereof A refresh circuit for refreshing a memory device is proposed. The refresh circuit includes: reading means for reading a set of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the memory c... | 08/26/2008 |
| 7417899 | Method of verifying flash memory device A method of verifying a flash memory device includes discharging memory cell strings respectively connected to an even bit line and an odd bit line. Next, a voltage is applied to the memory cell strings respectively connected to the even bit line and the odd bit lin... | 08/26/2008 |
| 7414902 | Semiconductor memory device with information loss self-detect capability A semiconductor memory device, including a plurality of programmable memory cells each one adapted to be brought into one among at least a first status and a second status, said plurality of memory cells including memory cells intended to store data, and means for a... | 08/19/2008 |
| 7414895 | NAND flash memory cell programming A flash memory device, such as a NAND flash, having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells is ... | 08/19/2008 |
| 7411835 | Discharge circuit for a capacitive load A circuit arrangement for the defined discharge of a capacitive load includes a first connecting terminal for connection of the load, a second connecting terminal for application of a predetermined potential, and a third connecting terminal for application of a disc... | 08/12/2008 |
| 7408811 | NAND-type flash memory on an SOI substrate with a carrier discharging operation A semiconductor memory device includes: a semiconductor layer provided on an insulating substrate or an insulating layer; active areas each defined in the semiconductor layer with a device insulating film buried therein; and NAND cell units formed on the active area... | 08/05/2008 |
| 7405978 | Nonvolatile semiconductor memory device having bitlines extending from cell array in single direction A semiconductor memory device comprises a cell array including a plurality of memory cells. The semiconductor memory device further comprises a plurality of bitlines formed in a bit layer and connected to the plurality of memory cells, wherein the bitlines extend fr... | 07/29/2008 |
| 7405986 | Redundant wordline deactivation scheme A method and apparatus for reducing power consumption of a memory device. The method includes initiating a precharge operation. The precharge operation includes driving one or more bitlines to a precharge voltage. The method also includes identifying one or more def... | 07/29/2008 |
| 7403442 | Pulse controlled word line driver The invention relates to a driver circuit for driving a word line of a memory. The driver circuit comprises a driver unit for deactivating the word line after an access to a memory cell, a discharging means for discharging the word line, and a signal generator that ... | 07/22/2008 |
| 7403423 | Sensing scheme for low-voltage flash memory Single-ended sensing devices for sensing a programmed state of a non-volatile memory cell are adapted for use in low-voltage memory devices. Methods of their operation include precharging an input node of a single-ended sensing device to a precharge potential while ... | 07/22/2008 |
| 7403420 | Flash memory device and associated recharge method A flash memory device comprises first and second mat structures connected to respective first and second high voltage lines, and a switch circuit connected between the first and second high voltage lines. The switch circuit supplies a program voltage from the first ... | 07/22/2008 |
| 7397701 | Method and apparatus for operating a string of charge trapping memory cells An array of charge trapping nonvolatile memory cells is arranged in several columns of cells, each arranged in a series, such as a NAND string. Each cell stores no more than a single charge storage state. ... | 07/08/2008 |
| 7394700 | Programming methods for a nonvolatile memory device using a Y-scan operation during a verify read operation Some embodiments of the present invention provide programming operations for reducing a program time for a nonvolatile memory device. A nonvolatile semiconductor memory device is programmed by receiving data to be programmed into memory cells from a host, programmin... | 07/01/2008 |
| 7394699 | Sense amplifier for a non-volatile memory device The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the bitline's precharge status. A biasing transistor is coupled to the feedback transistor. The biasing tran... | 07/01/2008 |
| 7391639 | Memory device and method for reading data A memory with memory cells, wherein a memory cell includes a resistive element and a switch, wherein the memory cells are connected with a common plate line and with respective bit lines, wherein the common plate line supplies a plate voltage, wherein the switches i... | 06/24/2008 |
| 7388789 | NAND memory device and programming methods A NAND Flash memory device is described that can reduce circuitry noise during program operations. The memory includes bit lines that can be electrically coupled together to charge share their respective voltage potentials prior to performing a discharge operation o... | 06/17/2008 |
| 7388790 | Semiconductor memory device and dynamic latch refresh method thereof A semiconductor integrated circuit device includes dynamic latches, switch circuit, capacitor, first static latch, and first transfer gate. In refreshing data of the dynamic latches, data stored in the first static latch is moved to the second node through the first... | 06/17/2008 |
| 7388799 | Semiconductor memory device A semiconductor memory device for consuming a uniform amount of current includes a memory cell block including a N normal wordline and a M preliminary wordline; a refresh address counting block for outputting a refresh address, having a plurality of bits, correspond... | 06/17/2008 |
| 7385868 | Method of refreshing a PCRAM memory device A method for refreshing PCRAM cells programmed to a low resistance state and entire arrays of PCRAM cells uses a simple refresh scheme which does not require separate control and application of discrete refresh voltages to the PCRAM cells in an array. Specifically, ... | 06/10/2008 |
| 7385848 | Semiconductor storage device and electronic equipment A semiconductor storage device has a memory cell array composed of a plurality of arrayed memory cells, word lines, bit lines, a bit line charging and discharging circuit, and a readout section. Each memory cell has two storage regions in vicinity of opposite ends o... | 06/10/2008 |
