Class 365/185.16 - Virtual ground

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter under 185.05 wherein all of the memory cells
No. of patents: 342
Last issue date: 03/20/2012

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Number	Title	Issue Date
8139416	Operation methods for memory cell and array for reducing punch through leakage A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the...	03/20/2012
8120960	Method and apparatus for accessing a non-volatile memory array comprising unidirectional current flowing multiplexers A non-volatile memory (NVM) having an array of memory cells and a unidirectional multiplexer (UMUX), the UMUX may be comprised of two or more address line ports adapted to receive addressing signals corresponding with elements in the memory array, and a set of switc...	02/21/2012
7974127	Operation methods for memory cell and array for reducing punch through leakage A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the...	07/05/2011
7929347	Compact virtual ground diffusion programmable ROM array architecture, system and method A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair o...	04/19/2011
7826267	Method and apparatus for reading and programming a non-volatile memory cell in a virtual ground array A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. In the dynamic read operation the global bit lines and the associated local bit lines are connected to a precharged volta...	11/02/2010
7706185	Reading circuitry in memory A reading circuit in a memory having a first memory cell coupled to a first bit line and a second bit line and a second memory cell coupled to the second bit line and a third bit line, is provided. The reading circuitry comprises a source side sensing circuit, a dra...	04/27/2010
7630243	Semiconductor memory device A virtual ground type semiconductor memory device comprises: a memory cell array in which nonvolatile memory cells each including a first electrode, a pair of second electrodes, and a charge retention part are arranged in row and column directions like a matrix; a r...	12/08/2009
7619925	Virtual ground array memory and programming method thereof A method for programming a virtual ground array memory, which includes a first cell and a second cell adjacent to first cell, includes the following steps. First, the first cell is selected as a target cell, wherein the second cell has been programmed to have data. ...	11/17/2009
7616488	Current or voltage measurement circuit, sense circuit, semiconductor non-volatile memory, and differential amplifier In a wire pair 120 including a first signal line 120a and a second signal line 120b, the first signal line 120a and the second signal line 120b are laid out so that they have substantially the same stray...	11/10/2009
7613042	Decoding system capable of reducing sector select area overhead for flash memory Methods and apparatus are disclosed for erasing memory cells in a virtual ground memory core, wherein a row decoder apparatus employs a protective voltage to wordlines of a sector of cells while concurrently providing an erase voltage to selected wordlines of the sa...	11/03/2009
7483302	Non-volatile memory device and method of compensating leakage reading current of a non-volatile memory array A non-volatile memory package includes a non-volatile memory array having a plurality of transistors that are electrically coupled in series, each of the transistors having an input terminal and an output terminal such that the output terminal of one of the transist...	01/27/2009
7436690	Flat cell read only memory using common contacts for bit lines and virtual ground lines In a flat cell read only memory, two bit lines or two virtual ground lines share a common contact such that the contact is slightly adjustable in its location for inserting a local metal word line without increasing the layout area to improve the reading speed of th...	10/14/2008
7400529	Non-volatile memory cell and non-volatile memory device using said cell A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insu...	07/15/2008
7376013	Compact virtual ground diffusion programmable ROM array architecture, system and method A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array having M rows and N columns. A shared source line is associated with ea...	05/20/2008
7359239	Non-volatile memory device having uniform programming speed Flash memory devices having a cell string structure. According to the present invention, the size of a first group of memory cells connected to a first word line and a second group of memory cells connected to a last word line is formed greater than that of a third ...	04/15/2008
7355897	Methods to resolve hard-to-erase condition in charge trapping non-volatile memory A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a ...	04/08/2008
7352626	Voltage regulator with less overshoot and faster settling time A voltage regulator may include an operational-amplifier section, a capacitor connected to an output of the operational-amplifier section, and a switch configured to connect the capacitor to a voltage supply. The switch is configured to charge the capacitor before a...	04/01/2008
7348640	Memory device A memory capable of reducing the memory cell size is provided. In this memory, a first gate electrode of a first selection transistor and a second gate electrode of a second selection transistor are provided integrally with a word line, and arranged to obliquely ext...	03/25/2008
7345917	Non-volatile memory package and method of reading stored data from a non-volatile memory array A non-volatile memory package includes a non-volatile memory array having a plurality of transistors that are electrically coupled in series, each of the transistors having an input terminal and an output terminal such that the output terminal of one of the transist...	03/18/2008
7345916	Method and apparatus for high voltage operation for a high performance semiconductor memory device A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuo...	03/18/2008
7327607	Method and apparatus for operating nonvolatile memory cells in a series arrangement A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge stora...	02/05/2008
7323742	Non-volatile memory integrated circuit A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells str...	01/29/2008
7324378	Method of driving a program operation in a nonvolatile semiconductor memory device In an embodiment, a method of driving a program operation in a nonvolatile semiconductor memory device is operable without discharging a bitline connected to a memory cell to be programmed between a program period and a verifying period. This remarkably improves pro...	01/29/2008
7324384	Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can...	01/29/2008
7324376	Method and apparatus for operating nonvolatile memory cells in a series arrangement A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge stora...	01/29/2008
7324377	Apparatus and method for programming and erasing virtual ground EEPROM without disturbing adjacent cells A method is described for erasing a selected data region in an NROM cell that is a member of a virtual ground NROM EEPROM array. The method provides that erasing the selected data region does not disturb the program state of unselected data regions. ...	01/29/2008
7317639	Two-bit charge trap nonvolatile memory device and methods of operating and fabricating the same Two-bit programmable nonvolatile memory devices and methods of operating and fabricating the same are provided. The device comprises a plurality of device isolation layers, a plurality of word lines crossing over the device isolation layers, and a multiple insulatio...	01/08/2008
7314798	Method of fabricating a nonvolatile storage array with continuous control gate employing hot carrier injection programming A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the tr...	01/01/2008
7307893	Semiconductor device and method for controlling the same A semiconductor memory device has a read ground and a write ground, these grounds being separately provided. Even when the read and verify operations are simultaneously executed, the source potential of an involved memory cell obtained at this time is equal to that ...	12/11/2007
7298651	Architecture for virtual ground memory arrays The drain programming window in virtual ground memory arrays may be enlarged by reducing the number of voltage drops in the cell access path. This reduction may be accomplished by reducing the number of transistors in the access path or by otherwise reducing the res...	11/20/2007
7294880	Semiconductor non-volatile memory cell with a plurality of charge storage regions For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical...	11/13/2007
7295475	Flash memory programming using an indication bit to interpret state Non-volatile memory, such as Flash memory, is programmed by writing a window of information to memory. The programmed/non-programmed state of each memory cell may be dynamically determined for each window and stored as an indication bit. These techniques can provide...	11/13/2007
7295471	Memory device having a virtual ground array and methods using program algorithm to improve read margin loss A program verification method for a memory device having a virtual array including a plurality of memory cells determines if leakage current passes through one or more neighboring memory cells to the programmed memory cell. The programmed memory cell is verified bas...	11/13/2007
7286398	Semiconductor device and method of controlling said semiconductor device A semiconductor device includes: groups of memory cells that are connected to word lines; and select gates that are controlled by control word lines and are connected to the groups of memory cells, each of the select gates being capable of storing protection informa...	10/23/2007
7283391	Semiconductor memory device A semiconductor memory device comprises: a plurality of memory elements; at least one bit line, wherein a memory operation is performed via at least a portion of the bit line with respect to at least one of the plurality of memory elements; and a load resistance reg...	10/16/2007
7282442	Contact hole structure of semiconductor device and method of forming the same A method of forming a contact hole of a semiconductor device, the method comprising: forming a gate line and a source/drain region in a substrate; depositing an etch stopper layer on the substrate; depositing a first interlayer dielectric layer on the etch stopper l...	10/16/2007
7283399	Nonvolatile memory system, semiconductor memory, and writing method A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing oper...	10/16/2007
7282401	Method and apparatus for a self-aligned recessed access device (RAD) transistor gate A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and...	10/16/2007
7280400	Reducing sneak currents in virtual ground memory arrays In a virtual ground memory array, sneak currents between input/output groups of sensed cells may be reduced by providing at least one column of programmed cells between the input/output groups. The sneak currents may arise when cells in each of two adjacent I/O grou...	10/09/2007
7277324	Driving method of nonvolatile memory and nonvolatile memory used in the same method To increase a cell current ratio of a program state to an erase state of two bit storage nonvolatile memory cells and reduce power consumption, a program state of MONOS-typed memory cells is a state where electrons are injected into two local regions near drain and ...	10/02/2007

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Class 365/185.16 - Virtual ground