Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 8094501 | Semiconductor memory device which includes memory cell having charge accumulation layer and control gate A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word... | 01/10/2012 |
| 8072810 | Program and erase methods with substrate transient hot carrier injections in a non-volatile memory The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN t... | 12/06/2011 |
| 7881112 | Program and erase methods with substrate transient hot carrier injections in a non-volatile memory The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN t... | 02/01/2011 |
| 7782673 | Semiconductor memory device which includes memory cell having charge accumulation layer and control gate A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word... | 08/24/2010 |
| 7778080 | Flash memory array system including a top gate memory cell A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included... | 08/17/2010 |
| 7663921 | Flash memory array with a top gate line dynamically coupled to a word line Systems and methods are disclosed including memory cells arranged in sectors. In one exemplary implementation, each memory cell may include a top gate, a source, a top gate line coupling memory cells in a sector, and a word line coupling memory cells together. Moreo... | 02/16/2010 |
| 7626863 | Flash memory array system including a top gate memory cell A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included... | 12/01/2009 |
| 7619924 | Device and method for reading out memory information A device for reading out memory information storable in a memory has an integrator and a comparator. The memory provides, in a hold phase, a leakage current, and in a readout phase, a readout current. The readout current is dependent on the stored memory information... | 11/17/2009 |
| 7567458 | Flash memory array having control/decode circuitry for disabling top gates of defective memory cells A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included... | 07/28/2009 |
| 7447073 | Method for handling a defective top gate of a source-side injection flash memory array A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included... | 11/04/2008 |
| 7423906 | Integrated circuit having a memory cell A memory cell having a programmable solid state electrolyte layer, a writing line and a controllable switch that is arranged between the solid state electrolyte layer and the writing line. The controllable switch has a control input that is connected with a selectin... | 09/09/2008 |
| 7420842 | Method of programming a three-terminal non-volatile memory element using source-drain bias A storage transistor is programmed as a non-volatile memory element by biasing the source and drain while a programming voltage is applied to the gate. The substrate is held at a different potential than the source/drain to insure that the greatest difference in vol... | 09/02/2008 |
| 7414894 | Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance A number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the grou... | 08/19/2008 |
| 7405969 | Non-volatile memory cell and non-volatile memory devices A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a nonconducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insul... | 07/29/2008 |
| 7359239 | Non-volatile memory device having uniform programming speed Flash memory devices having a cell string structure. According to the present invention, the size of a first group of memory cells connected to a first word line and a second group of memory cells connected to a last word line is formed greater than that of a third ... | 04/15/2008 |
| 7355243 | Flash memory device and method for fabricating the same A flash memory device including an isolation layer for defining active regions in a semiconductor substrate. The active region is a region in which flash memory cells are to be formed. The device also includes a gate stack is formed to come across the active region ... | 04/08/2008 |
| 7349251 | Integrated memory circuit arrangement A memory circuit arrangement includes a switching element per column that can be used to connect or disconnect two bit lines for memory cells of a column. The switching element leads to a reduction of the chip area and/or to an improvement in the electronic properti... | 03/25/2008 |
| 7336539 | Method of operating flash memory cell A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked g... | 02/26/2008 |
| 7333382 | Method and apparatus for an oscillator within a memory device An apparatus for controlling generation of pulses for refresh operations of a memory device having a pad to transfer information and to receive signals from an external interface. The apparatus includes a switch, coupled to a current source and to the pad receiving ... | 02/19/2008 |
| 7332768 | Non-volatile memory devices Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, program... | 02/19/2008 |
| 7317634 | Nonvolatile semiconductor memory device The programming speed of a nonvolatile semiconductor memory device used as a flash memory is increased as follows. First, second, and third assist gates, a control gate, as well as first and second storage nodes are created over a p-type well. In the course of a pro... | 01/08/2008 |
| 7311385 | Micro-fluid ejecting device having embedded memory device A semiconductor substrate for a micro-fluid ejecting device. The semiconductor substrate includes a plurality of fluid ejection devices disposed on the substrate. A plurality of driver transistors are disposed on the substrate for driving the plurality of fluid ejec... | 12/25/2007 |
| 7307882 | Non-volatile memory A non-volatile memory having a gate structure, a pair of storage units and two assist gates is provided. The gate structure is disposed on the substrate. The storage units are disposed on the sidewalls of the gate structure. The assist gates are disposed on the resp... | 12/11/2007 |
| 7283391 | Semiconductor memory device A semiconductor memory device comprises: a plurality of memory elements; at least one bit line, wherein a memory operation is performed via at least a portion of the bit line with respect to at least one of the plurality of memory elements; and a load resistance reg... | 10/16/2007 |
| 7271435 | Modified source/drain re-oxidation method and system Methods and devices are disclosed utilizing a phosphorous-doped oxide layer that is added prior to re-oxidation. This allows greater control of the re-oxidation process and greater control of the performance characteristics of semiconductor devices such as flash mem... | 09/18/2007 |
| 7272039 | Minimizing adjacent wordline disturb in a memory device A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predete... | 09/18/2007 |
| 7268385 | Semiconductor memory device A semiconductor memory device comprises diffusion regions, a floating gate, a third diffusion region, a selection gate electrode, and a control gate electrode that three-dimensionally crosses the selection gate electrode and extends in a direction orthogonal to the ... | 09/11/2007 |
| 7265409 | Non-volatile semiconductor memory A non-volatile semiconductor memory having a memory transistor including a stacked-layer film formed between a semiconductor substrate and a gate electrode and having a charge storage ability, a first conductivity type region of the semiconductor substrate in which ... | 09/04/2007 |
| 7262463 | Transistor including a deposited channel region having a doped portion A transistor having a gate electrode, a source electrode, a drain electrode, a dielectric material and a channel region disposed between the source electrode and drain electrode. The channel region includes a portion doped with an impurity to change the fixed charge... | 08/28/2007 |
| 7259420 | Multiple-gate device with floating back gate Disclosed is a multiple-gate transistor that includes a channel region and source and drain regions at ends of the channel region. A gate oxide is positioned between a logic gate and the channel region and a first insulator is formed between a floating gate and the ... | 08/21/2007 |
| 7248504 | Data processing device A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a seco... | 07/24/2007 |
| 7244986 | Two-bit cell semiconductor memory device A 2-bit cell is made up of first and second diffusion regions provided on a substrate surface, first and second storage nodes adjacent to the first and second diffusion region, first and second gate electrodes provided on first and second storage nodes, a third stor... | 07/17/2007 |
| 7230847 | Substrate electron injection techniques for programming non-volatile charge storage memory cells A programming technique for a flash memory causes electrons to be injected from the substrate into charge storage elements of the memory cells. The source and drain regions of memory cells along a common word line or other common control gate line being programmed b... | 06/12/2007 |
| 7227234 | Embedded non-volatile memory cell with charge-trapping sidewall spacers An IC includes both “volatile” CMOS transistors (FETs) and embedded non-volatile memory (NVM) cells, both including polysilicon gate structures, sidewall oxide layers, sidewall spacer structures, and source/drain regions. The sidewall spacers of both the NVM cel... | 06/05/2007 |
| 7221586 | Memory utilizing oxide nanolaminates Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region b... | 05/22/2007 |
| 7221017 | Memory utilizing oxide-conductor nanolaminates Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A float... | 05/22/2007 |
| 7218570 | Apparatus and method for memory operations using address-dependent conditions An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative... | 05/15/2007 |
| 7202540 | Semiconductor memory device A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentr... | 04/10/2007 |
| 7199424 | Scalable flash EEPROM memory cell with notched floating gate and graded source region An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulat... | 04/03/2007 |
| 7196371 | Flash memory A method for fabricating a flash memory is described. A mask layer having openings to expose a portion of the substrate is formed on the substrate. A tunneling dielectric layer is formed at the bottom surface of the openings. Conductive spacers are formed on the sid... | 03/27/2007 |
