Class 365/185.14 - Program gate

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter under 185.05 wherein an additional insulated
No. of patents: 552
Last issue date: 04/24/2012

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Number	Title	Issue Date
8164954	Flash memory device and program method thereof A nonvolatile memory device that includes first and second storage areas, and a control logic configured to control the first and second storage areas, wherein when a program operation of the first storage area is passed before a program operation of the second stor...	04/24/2012
8159878	Semiconductor memory having both volatile and non-volatile functionality and method of operating Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type confi...	04/17/2012
8130568	Method of programming nonvolatile memory device A method of programming a nonvolatile memory device includes performing a first LSB program operation on memory cells coupled to a selected word line in order to store least significant bit (LSB) data in the memory cells, performing a first most significant bit (MSB...	03/06/2012
8085607	3-level non-volatile semiconductor memory device and method of driving the same A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to...	12/27/2011
8018770	Program and sense operations in a non-volatile memory device Methods for programming and sensing in a memory device, a data cache, and a memory device are disclosed. In one such method, all of the bit lines of a memory block are programmed or sensed during the same program or sense operation by alternately multiplexing the od...	09/13/2011
7974126	Semiconductor memory device including write selectors A semiconductor memory device includes: static memory cells arranged in a matrix; a read bit line for transmitting data read from one of the memory cells; a write bit line for transmitting data to be written to one of the memory cells; an input data line for transmi...	07/05/2011
7920424	Scalable electrically eraseable and programmable memory (EEPROM) cell array A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of t...	04/05/2011
7911843	Non-volatile memory device and program method thereof A method of programming a non-volatile memory device employing program loops. Each program loop comprises a programming operation and a subsequent plurality of verifying operations. The method includes preventing the next program loop based on the results of perform...	03/22/2011
7876619	Nonvolatile semiconductor memory device A semiconductor memory device comprises: a write circuit including a latch circuit configured by two inverters having a positive side power supply terminal supplied with a first voltage and a negative side power supply terminal supplied with a second voltage; and a ...	01/25/2011
7855917	Semiconductor memory device and driving method thereof The disclosure concerns a memory including a floating body provided in a semiconductor layer between a source and a drain and storing data; a first gate dielectric provided on a first surface of the body; a first gate electrode provided on the first surface via the ...	12/21/2010
7813203	Semiconductor memory device and method of manufacturing of the same A semiconductor memory device includes a plurality of active areas each extending in a first direction and including a memory cell string which includes select transistors and memory cells, current paths of which are connected in series, a first extension portion wh...	10/12/2010
7778079	Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices In a memory device and in a method of programming the same, a memory device comprises: a plurality of memory cells, each memory cell comprising a resistance-changeable material that has an initial resistance that is determined in response to an applied programming c...	08/17/2010
7773422	3-level non-volatile semiconductor memory device and method of driving the same A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to...	08/10/2010
7729170	Semiconductor device and its control method A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the...	06/01/2010
7701767	Strap-contact scheme for compact array of memory cells A semiconductor device with multiple strap-contact configurations for a memory cell array. An array with memory cells interconnected with bit-lines, control-gate lines, erase gate lines, common-source lines, and word-lines is provided. In one aspect of an illustrati...	04/20/2010
7602645	Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing same There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, circuitry and techniques for reading, writing and/or operating semiconductor memory cells of a memory cell array, including, for example, electricall...	10/13/2009
7593262	Memory structure and operating method thereof A method for operating memory used for enabling the memory device to have a first threshold voltage or a second threshold voltage is provided. The method includes the following procedures. First, an operating voltage is applied to a gate of the memory device for a f...	09/22/2009
7512004	Semiconductor memory device having stacked gate including charge accumulation layer and control gate and test method thereof A semiconductor memory device includes a memory cell, a word line, a bit line, a column gate, and a power supply decode circuit. The memory cell has a first MOS transistor including a charge accumulation layer and a control gate. The bit line is connected to a drain...	03/31/2009
7499325	Flash memory device with improved erase operation Some embodiments include a device having memory cells coupled to a well of a semiconductor substrate, and a select transistor coupled between the memory cells and a bit line of the device. The device may have a first circuit to raise a well voltage of the well from ...	03/03/2009
7471563	Semiconductor memory device Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isola...	12/30/2008
7471564	Trapping storage flash memory cell structure with inversion source and drain regions Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-Fin to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in ...	12/30/2008
7440311	Single-poly non-volatile memory cell A non-volatile memory cell includes a floating gate transistor having a floating gate coupled to a metal layer capacitor defined in one or more metal layers. Within each metal layer, the metal layer capacitor includes a first plate coupled to the floating gate and a...	10/21/2008
7436706	Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing same There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, circuitry and techniques for reading, writing and/or operating a semiconductor memory cells of a memory cell array, including electrically floating b...	10/14/2008
7436710	EEPROM memory device with cell having NMOS in a P pocket as a control gate, PMOS program/erase transistor, and PMOS access transistor in a common well A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a commo...	10/14/2008
7430134	Memory cell structure of SRAM Disclosed is an SRAM including a latch circuit, first and second write transfer gates, first and second write buffer transistors, read driver transistor, and read transfer gate. A write path is formed by connecting first and second write transfer gates and first and...	09/30/2008
7411828	Method and apparatus for programming single-poly pFET-based nonvolatile memory cells Methods and apparatuses for programming a single-poly pFET-based nonvolatile memory cell bias the cell so that band-to-band tunneling (BTBT) is induced and electrons generated by the BTBT are injected onto a floating gate of the cell. Following a predetermined event...	08/12/2008
7411838	Semiconductor memory device A drive circuit 22 controls voltages applied to a substrate 1, selection gates SG0 and SG1, a local bit line LB2, and a control gate CGn. By respectively applying a negative voltage to the control gate CGn, a positive voltage to th...	08/12/2008
7411836	Method of operating non-volatile memory A method of operating a non-volatile memory comprising a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer clos...	08/12/2008
7411829	Method and apparatus for programming single-poly pFET-based nonvolatile memory cells Methods and apparatuses for programming a single-poly pFET-based nonvolatile memory cell bias the cell so that band-to-band tunneling (BTBT) is induced and electrons generated by the BTBT are injected onto a floating gate of the cell. Following a predetermined event...	08/12/2008
7408809	Method and apparatus for programming single-poly pFET-based nonvolatile memory cells Methods and apparatuses for programming a single-poly pFET-based nonvolatile memory cell bias the cell so that band-to-band tunneling (BTBT) is induced and electrons generated by the BTBT are injected onto a floating gate of the cell. Following a predetermined event...	08/05/2008
7408804	Systems for soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells A set of non-volatile storage elements is divided into subsets for soft programming in order to more fully soft-program slower soft programming elements. The entire set of elements is soft-programmed until verified as soft programmed (or until a first subset of elem...	08/05/2008
7405971	Semiconductor device A semiconductor integrated circuit includes non-volatile memory elements (PM1, PM2), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshol...	07/29/2008
7382654	Trapping storage flash memory cell structure with inversion source and drain regions Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-FIN to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in ...	06/03/2008
7372734	Methods of operating electrically alterable non-volatile memory cell A nonvolatile memory cell is provided. The memory cell includes a storage transistor and an injector in a well of an n-type conductivity. The well is formed in a semiconductor substrate of a p-type conductivity. The storage transistor comprises a source, a drain, a ...	05/13/2008
7372732	Pulse width converged method to control voltage threshold (Vt) distribution of a memory cell A method of operating on a plurality of non-volatile multi-level memory cells is disclosed. The memory cells have at least a first, second, third and fourth program level. Each of program levels corresponds to a different binary state and has a voltage threshold dis...	05/13/2008
7366024	Method and apparatus for operating a string of charge trapping memory cells A string of memory cells with a charge trapping structure is read, by selecting part of a memory cell selected by a word line. Part of the memory cell is selected by turning on one of the pass transistors on either side of the string of memory cells. The charge stor...	04/29/2008
7355894	Programming flash memories A flash memory device has an array of flash memory cells, a detector for detecting an external voltage applied to the flash memory device, and a command control circuit for controlling access to the array of flash memory cells. The command control circuit is adapted...	04/08/2008
7352018	Non-volatile memory cells and methods for fabricating non-volatile memory cells The invention relates to a method for fabricating stacked non-volatile memory cells. Further, the invention relates to stacked non-volatile memory cells. The invention particularly relates to the field of non-volatile NAND memories having non-volatile stacked memory...	04/01/2008
7352605	Nonvolatile ferroelectric memory device and method thereof A nonvolatile ferroelectric memory device has a plurality of ferroelectric memory cells. The ferroelectric memory cells include a first double gate cell for storing a bit of datum, the first double gate cell including a ferroelectric layer and a floating channel lay...	04/01/2008
7350433	Transmission control system A transmission control system for maintaining good positioning performance even if a dynamic characteristic of a transmission is out of a predicted range. A sliding mode controller provided in a shift controller has two degrees of freedom and can independently speci...	04/01/2008

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Class 365/185.14 - Program gate