Bizarre Patents
Wearable Device For Feeding and Observing Birds and Other Flying Animals
A device for feeding and observing flying animals comprising a hat, a support mounted on the hat and extending outward from the hat, and a feeder mounted on the support.
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| Number | Title | Issue Date |
| 8139415 | Phase-change memory device A phase-change memory device is capable of reducing current consumption and preventing performance deterioration caused due to line load by improving a process of selecting memory cells for a write/read operation. The phase-change memory device has a plurality of ce... | 03/20/2012 |
| 8125829 | Biasing system and method Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and a voltage source coupled to the global line and configured to output a bias voltage on the global line whe... | 02/28/2012 |
| 8120959 | NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same A nonvolatile memory device includes a nonvolatile memory array including a plurality of charge retaining transistors arranged in rows and columns. The device has a plurality source lines formed in parallel with the bit lines associated with each column. Row decode/... | 02/21/2012 |
| 8111553 | Non-volatile semiconductor memory device in which program disturb is reduced and method of programming the same A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a... | 02/07/2012 |
| 8098525 | Pre-charge sensing scheme for non-volatile memory (NVM) The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-... | 01/17/2012 |
| 8064259 | Nonvolatile NAND-type memory devices including charge storage layers connected to insulating layers A nonvolatile memory device includes a word line group including a plurality of middle word lines and an edge word line having charge storage patterns on a substrate. A peripheral line is disposed on one side of the word line group so that the edge word line is betw... | 11/22/2011 |
| 8009476 | Semiconductor memory device using variable resistor Example embodiments relate to a variable resistance semiconductor memory device including: a plurality of memory blocks belonging to different memory sectors and alternately arranged in a memory bank including the memory sectors so as to be adjacent to each other; a... | 08/30/2011 |
| 8004899 | Memory array and method of operating a memory A memory array is shown, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of t... | 08/23/2011 |
| 7983085 | Memory array with inverted data-line pairs At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is coupled... | 07/19/2011 |
| 7957191 | Method of programming non-volatile memory device A method of programming a non-volatile memory device includes applying a power supply voltage to a drain select line, applying a high level voltage to a drain-side pass word line or a source-side pass word line, and applying a pass voltage to unselected word lines a... | 06/07/2011 |
| 7889556 | Flash memory having insulating liners between source/drain lines and channels A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie betwee... | 02/15/2011 |
| 7872915 | Nonvolatile memory device and reading method thereof A nonvolatile memory device can improve its operation characteristic by reducing leakage current of a bit line in a read operation. The nonvolatile memory device includes a plurality of word lines, a plurality of main bit lines intersecting with the plurality of wor... | 01/18/2011 |
| 7826266 | Semiconductor device having global and local data lines coupled to memory mats A semiconductor device includes a sense amplifier and a decoder provided on a semiconductor substrate together with memory cells provided above the sense amplifier and the decoder. Each of the memory cells includes a channel region, in which current flows in a direc... | 11/02/2010 |
| 7821833 | Semiconductor device and its control method A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the... | 10/26/2010 |
| 7668011 | Serial flash memory device and precharging method thereof Provided herein is a serial flash memory device and precharging method thereof in which a single local bit-line data is sensed in synchronization with a clock. The method includes precharging two or more local bit-lines in synchronization with a first clock; and dis... | 02/23/2010 |
| 7668010 | Flash memory having insulating liners between source/drain lines and channels A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie betwee... | 02/23/2010 |
| 7656708 | Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations The present invention provides a solution for long master bit lines in a large capacity memory device. A master bit line is partitioned by at least one switching transistor placed on the master bit line. ... | 02/02/2010 |
| 7643345 | Semiconductor memory device which includes stacked gate having charge accumulation layer and control gate A semiconductor memory device includes memory cells, a memory cell array, a contact region, and first contact plugs. The memory cells include a control gate and a current path. The memory cells are arranged in the memory cell array in the first direction. The contac... | 01/05/2010 |
| 7643344 | Variable resistive memory A variable resistive memory device includes memory sectors, memory cells in each of the memory sectors, sub-wordlines including a first in signal communication with at least a first pair of the memory cells in a first sector and a second in signal communication with... | 01/05/2010 |
| 7626862 | Semiconductor memory device A semiconductor memory device comprises a memory cell array having a hierarchical word line structure including main word lines and sub-word lines; a main word driver for driving a non-selected main word line to high and for driving and activating a selected main wo... | 12/01/2009 |
| 7619923 | Apparatus for reducing leakage in global bit-line architectures A circuit for reducing current leakage in hierarchical bit-line architectures includes a sense amplifier having transistors, the sense amplifier coupled to bit-lines of cells in a memory array, the sense amplifier configured for detecting stored data from one of the... | 11/17/2009 |
| 7616487 | Decoders and decoding methods for nonvolatile semiconductor memory devices A decoder for a non-volatile semiconductor memory device includes a level shifter configured to generate a negative first voltage at an output thereof responsive to a first state of a global word line and to generate a second voltage more positive than the first vol... | 11/10/2009 |
| 7577032 | Non-volatile semiconductor memory device The local row decoder includes a first MOS transistor of a first conductivity type having one end connected to the local word line, the other end supplied with a first voltage, and a gate connected to the global word line, and a second MOS transistor of a second con... | 08/18/2009 |
| 7573752 | NAND flash memory cell programming A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor mem... | 08/11/2009 |
| 7495958 | Program and erase methods and structures for byte-alterable flash memory An array of flash memory cells arranged in a plurality of rows and a plurality of columns includes a first row comprising a plurality of units. Each unit includes a plurality of flash memory cells, an erase-gate line connecting erase-gates of all flash memory cells ... | 02/24/2009 |
| 7443725 | Floating gate isolation and method of making the same The present invention relates to a method for forming a set of floating gates which are isolated from each other by means of slits, as well as semiconductor devices using the floating gate. The present invention provides a method for manufacturing an array of semico... | 10/28/2008 |
| 7430150 | Method and system for providing sensing circuitry in a multi-bank memory device A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The metho... | 09/30/2008 |
| 7428168 | Semiconductor memory device sharing a data line sense amplifier and a write driver in order to reduce a chip size A semiconductor memory device includes a first and a second bank, a global data line, a first and a second data line, a data transmitter, and a switch. The global data line is configured between the first and the second banks and commonly shared by the first and the... | 09/23/2008 |
| 7426129 | Layout structures in semiconductor memory devices including bit line layout for higher density migration A true bit line can extend across a memory cell area of the memory device in a first direction and a complementary bit line can extend across the memory cell area in a second direction opposing the first direction, wherein the true bit line and the complementary bit... | 09/16/2008 |
| 7414895 | NAND flash memory cell programming A flash memory device, such as a NAND flash, having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells is ... | 08/19/2008 |
| 7407819 | Polymer memory having a ferroelectric polymer memory material with cell sizes that are asymmetric A polymer memory and its method of manufacture are provided. One multi-layer construction of the polymer memory has two sets of word lines and a set of bit lines between the word lines. The word lines of each set of word lines have center lines that are spaced by a ... | 08/05/2008 |
| 7403427 | Method and apparatus for reducing stress in word line driver transistors during erasure In a method of erasing flash memory cells, the flash memory cells organized in selectable memory blocks, the erasing step comprising applying an erase pulse voltage to a commonly biased cell well of at least one selected and at least one unselected memory blocks, th... | 07/22/2008 |
| 7379375 | Memory circuits having different word line driving circuit configurations along a common global word line and methods for designing such circuits Memory circuits having different configurations of local word line driving circuits (LWLDC) and methods for designing such circuits are provided. The memory circuits include an array of memory cells and a plurality of local word lines each coupled to a different sub... | 05/27/2008 |
| 7379345 | Nonvolatile semiconductor memory device that achieves speedup in read operation A plurality of first sub-bit lines are each connected to a common source line via a corresponding first sub-bit line reset transistor with NMOS structure, and a plurality of second sub-bit lines are each connected to the common source line via a corresponding second... | 05/27/2008 |
| 7366025 | Reduced power programming of non-volatile cells Methods for minimizing current consumption in a memory array during programming of non-volatile memory cells, such as NROM cells, in the array include: programming a cell without having a direct current flowing from a positive supply to ground through the array, pro... | 04/29/2008 |
| 7366401 | Video summary play apparatus and method A signal receiving unit receives a signal including video data. A video data memory sequentially stores the video data. A timing decision unit decides a timing to generate a video summary by referring to the signal, and provides a generation request of the video sum... | 04/29/2008 |
| 7359240 | Flash memory device with multi level cell and burst access method therein A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and ... | 04/15/2008 |
| 7355891 | Fabricating bi-directional nonvolatile memory cells A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening se... | 04/08/2008 |
| 7349251 | Integrated memory circuit arrangement A memory circuit arrangement includes a switching element per column that can be used to connect or disconnect two bit lines for memory cells of a column. The switching element leads to a reduction of the chip area and/or to an improvement in the electronic properti... | 03/25/2008 |
| 7349033 | Systems and methods for correcting color phase error in video systems Systems and methods are provided for correcting color phase error in a video decoder system. A demodulator system demodulates the composite input signal and the at least one delayed signal to produce sets of baseband chroma components based on a phase correction val... | 03/25/2008 |
