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| Number | Title | Issue Date |
| 8179722 | Page buffer circuit and nonvolatile memory device A page buffer circuit comprises a sense amplification unit configured to compare a reference voltage and a bit line voltage of a bit line of a selected memory block and to increase a voltage level of a sense node by a difference between the reference voltage and the... | 05/15/2012 |
| 8174888 | Page-buffer and non-volatile semiconductor memory including page buffer In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit... | 05/08/2012 |
| 8144516 | Dynamic pass voltage for sense operation in a memory device Methods for sensing and memory devices are disclosed. One such method for sensing uses a dynamic pass voltage on at least one adjacent memory cell that is adjacent to a selected memory cell for programming. If the adjacent memory cell is not programmed, the pass vol... | 03/27/2012 |
| 8139414 | Source side asymmetrical precharge programming scheme A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND... | 03/20/2012 |
| 8134872 | Apparatus and methods for programming multilevel-cell NAND memory devices Methods and apparatus are provided. A first data value is read from a first memory cell and is stored. An attempt is made to add a second data value to the first memory cell. If the attempt to add the second data value to the first memory cell is unsuccessful, the f... | 03/13/2012 |
| 8125828 | Page buffer circuit with reduced size and methods for reading and programming data with the same A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the da... | 02/28/2012 |
| 8107294 | Read mode for flash memory A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command inclu... | 01/31/2012 |
| 8094500 | Non-volatile memory and method with write cache partitioning A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriente... | 01/10/2012 |
| 8068365 | Non-volatile memory device having configurable page size A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively ac... | 11/29/2011 |
| 8004898 | Nonvolatile memory device, program method thereof, and memory system including the same A nonvolatile memory device may include a memory cell array adapted to store tail-bit flag information indicating tail-bit memory cells, and a tail-bit controller adapted to calibrate a program start voltage of normal memory cells and a program start voltage of the ... | 08/23/2011 |
| 7969782 | Determining memory page status The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status of a page of memory cells without using input/output (I/O) circuitry, and outputting the status through the... | 06/28/2011 |
| 7916542 | Nonvolatile memory device with multiple page regions, and methods of reading and precharging the same A nonvolatile memory device includes a memory cell array having multiple memory cells arranged at intersections of word lines and bit lines, a first page region configured with at least two adjacent memory cells coupled to a word line, and a second page region confi... | 03/29/2011 |
| 7889555 | Flash memory system capable of operating in a random access mode and data reading method thereof A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory c... | 02/15/2011 |
| 7885113 | Method of controlling a program control of a flash memory device A flash memory device and method of controlling a program operation thereof, includes page buffers divided into a predetermined number of groups and a program operation is performed on a group basis. ... | 02/08/2011 |
| 7885112 | Nonvolatile memory and method for on-chip pseudo-randomization of data within a page and between pages Features within an integrated-circuit memory chip enables scrambling or randomization of data stored in an array of nonvolatile memory cells. In one embodiment, randomization within each page helps to control source loading errors during sensing and floating gate to... | 02/08/2011 |
| 7881110 | Method of programming nonvolatile memory device The present invention relates to a method of programming a nonvolatile memory device. A method of programming a nonvolatile memory device in accordance with an aspect of the present invention can include performing a program operation on a first page, counting a pro... | 02/01/2011 |
| 7881111 | Semiconductor memory having electrically erasable and programmable semiconductor memory cells An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level st... | 02/01/2011 |
| 7848144 | Reverse order page writing in flash memories To store, in a memory block whose word lines are written successively in a word line writing order, a plurality of data pages that are ordered by logical page address, the pages are written to the word lines so that every page that is written to any one of the word ... | 12/07/2010 |
| 7830712 | Non-volatile memory apparatus for controlling page buffer and controlling method thereof A non-volatile memory apparatus for controlling a page buffer includes a page buffer configured to include a plurality of buffer stages, each buffering input/output data of cell arrays in units of predetermined number of bits, and a control unit configured to select... | 11/09/2010 |
| 7826265 | Memory device with variable trim setting A memory device includes a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one associated trim parameter. The trim parameter for each subset is stored in the memory array within the associated ... | 11/02/2010 |
| 7817472 | Operating method of memory device An operating method of a memory array is provided. The operating method includes performing a programming operation. The programming operation is performed by applying a first voltage to a bit line of the memory array and a second voltage to a plurality of word line... | 10/19/2010 |
| 7813178 | Semiconductor memory device and write control method therefor Disclosed is a semiconductor memory device which includes a read data latch that holds read data from a phase change memory and latches write data entered from outside and holds write data entered from outside, a write data latch that holds the write data for a cell... | 10/12/2010 |
| 7808825 | Non-volatile memory device and method of programming the same When performing a program operation, a non-volatile memory device comprising a multi-plane performs a cache write operation by employing a page buffer circuit of a plane that does not perform the program operation. A data line mux transfers an externally input first... | 10/05/2010 |
| 7796431 | Page buffer used in a NAND flash memory and programming method thereof A page buffer used in a NAND flash memory comprises a first latch circuit, a second latch circuit, a bit line voltage supply circuit and a verification circuit comprising a first verification path, a second verification path and a third verification path. The first ... | 09/14/2010 |
| 7787300 | Memory devices with page buffer having dual registers and method of using the same A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifie... | 08/31/2010 |
| 7764546 | Method and architecture for fast flash memory programming Embodiments of the present invention disclose a method of utilizing a flash memory array to decrease programming time while maintaining sufficient read speeds. An array of cells is programmed and read in pages that are oriented in the column direction, parallel to t... | 07/27/2010 |
| 7755945 | Page buffer and method of programming and reading a memory A page buffer and method of programming and reading a memory are provided. The page buffer includes a first latch, a second latch, a data change unit and a program control unit. The first latch includes a first terminal for loading data of the lower page and the upp... | 07/13/2010 |
| 7751243 | Semiconductor memory device provided with MOS transistor having charge accumulation layer and control gate and data write method of NAND flash memory A semiconductor memory device includes a memory cell group, a selection transistor, a page buffer, and a row decoder. The memory cell group includes memory cell transistors connected in series. The selection transistor is connected to the memory cell transistor. The... | 07/06/2010 |
| 7751242 | NAND memory device and programming methods A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines of an array row are concurrently programmed as a common page. Floating gate coupling during programming c... | 07/06/2010 |
| 7724575 | Page-buffer and non-volatile semiconductor memory including page buffer In one aspect a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit ... | 05/25/2010 |
| 7719893 | Nonvolatile memory and apparatus and method for deciding data validity for the same Provided are a nonvolatile memory and an apparatus and method for deciding data validity for the same, in which validity of data stored in the nonvolatile memory can be decided. The nonvolatile memory includes a memory cell storing data bits in a plurality of pages ... | 05/18/2010 |
| 7706184 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device includes a memory cell array having a plurality of word lines and a plurality of bit lines, and at least first and second page buffers to which the plurality of bit lines are connected. The plurality of word lines are divide... | 04/27/2010 |
| 7706183 | Read mode for flash memory A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command inclu... | 04/27/2010 |
| 7701765 | Non-volatile multilevel memory cell programming The present disclosure includes methods, devices, modules, and systems for programming multilevel non-volatile memory cells, each cell having a number of lower pages and an upper page,. One method includes programming a first lower page, programming a second lower p... | 04/20/2010 |
| 7701766 | Non-volatile memory device and method of programming in the same A non-volatile memory device according to one example embodiment of the present invention includes a page buffer configured to have a first register for receiving data and storing temporarily the received data to be inputted to a pair of first bit lines, a second re... | 04/20/2010 |
| 7675777 | Non-volatile semiconductor memory device using adjacent bit lines for data transmission and method of driving the same A non-volatile semiconductor memory device, including a memory array having a plurality of first bit line groups and a plurality of second bit line groups that are alternately arranged to be adjacent each other, a plurality of data lines, a plurality of first page b... | 03/09/2010 |
| 7663920 | Memory system and data reading and generating method An object of the present invention is to provide a memory system that offers enhanced security of ROM code that is data whose contents can be utilized for a given purpose in its intact form. In a memory system, data is read from a memory according to at least two or... | 02/16/2010 |
| 7649776 | Nonvolatile semiconductor memory system According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data betwee... | 01/19/2010 |
| 7639537 | Method for writing data in a non volatile memory unit A method for writing data in a non volatile memory unit having memory pages includes a predetermined number of memory cells storing a memory word being a predetermined sequence of digital values. An erase operation erases the memory words in the memory page, setting... | 12/29/2009 |
| 7619922 | Method for non-volatile memory with background data latch caching during erase operations Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to per... | 11/17/2009 |
