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| Number | Title | Issue Date |
| 8189390 | NAND flash architecture with multi-level row decoding A NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select a block, for example. The seco... | 05/29/2012 |
| 8174912 | Systems and methods for circular buffering control in a memory device Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, memory devices are disclosed that include a plurality of non-volatile memory blocks, and a memory write circuit. The memory write... | 05/08/2012 |
| 8169826 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device comprises: a plurality of first memory strings; a first select transistor having one end thereof connected to one end of the first memory strings; a first line commonly connected to the other end of a plurality of the first ... | 05/01/2012 |
| 8149621 | Flash memory device and method of testing the flash memory device A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit includi... | 04/03/2012 |
| 8149620 | Flash memory device having dummy cell A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured ... | 04/03/2012 |
| 8144515 | Interleaved flash storage system and method A flash storage system accesses data interleaved among flash storage devices. The flash storage system receives a data block including data portions, stores the data portions in a data buffer, and initiates data transfers for asynchronously writing the data portions... | 03/27/2012 |
| 8139413 | Flash memory device A flash memory device can include a memory cell array that includes a plurality of memory blocks, where each of the memory blocks has memory cells arranged at intersections of word lines and bit lines, where ones of the plurality of memory blocks are immediately adj... | 03/20/2012 |
| 8130550 | Memory with sub-blocks A non-volatile memory comprising a NOR block with a first sub-block independently addressable from a second sub-block, the two sub-blocks sharing a physical substrate of the NOR block, and a first memory to store execution status information to reflect an erase stat... | 03/06/2012 |
| 8120958 | Multi-die memory, apparatus and multi-die memory stack The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a com... | 02/21/2012 |
| 8107293 | Semiconductor memory device A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of... | 01/31/2012 |
| 8107291 | Method of programming flash memory device A method of programming data in a flash memory device is disclosed. The memory device includes a memory cell array which in turn includes at least one block, and the block in turn includes a plurality of pages. A program command to program a plurality of pages in th... | 01/31/2012 |
| 8107292 | Three dimensional stacked nonvolatile semiconductor memory In a three dimensional stacked nonvolatile semiconductor memory according to the present invention, a first block has a selected first cell unit including a memory cell to be read and a non-selected second cell unit not including a memory cell to be read. A read pot... | 01/31/2012 |
| 8102711 | Three dimensional stacked nonvolatile semiconductor memory A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a... | 01/24/2012 |
| 8098524 | Semiconductor memory device capable of increasing writing speed A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word l... | 01/17/2012 |
| 8089810 | Semiconductor integrated circuit device for driving liquid crystal display The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An elec... | 01/03/2012 |
| 8085593 | Method of inputting address in nonvolatile memory device and method of operating the nonvolatile memory device A method of inputting address in a nonvolatile memory device includes inputting a row address including an information for selecting a memory block and an information for selecting a page, and inputting a column including an information for selecting a column and an... | 12/27/2011 |
| 8081512 | Non-volatile semiconductor memory device A non-volatile semiconductor memory device includes a non-volatile memory having a plurality of blocks each including a plurality of memory cells, a bit line electrically connected to one end of a current path of the memory cell, a source line electrically connected... | 12/20/2011 |
| 8077517 | Distributed VDC for SRAM memory An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to ... | 12/13/2011 |
| 8072809 | Nonvolatile semiconductor memory Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data... | 12/06/2011 |
| 8068364 | Three dimensional stacked nonvolatile semiconductor memory A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory... | 11/29/2011 |
| 8068363 | Flash memory apparatus and read operation control method therefor A flash memory apparatus of an embodiment is configured to include a flash memory including a plurality of blocks and a read operation control circuit determining whether to replace a block in accordance with the number of times a read process is performed for each ... | 11/29/2011 |
| 8059461 | Flash memory device The flash memory device includes a block switch, first and second cell strings, first and second source lines, drain contacts, and first and second source contacts. The first cell string is connected to a first bit line and a second cell string is connected to a sec... | 11/15/2011 |
| 8050095 | Flash memory data correction and scrub techniques In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid da... | 11/01/2011 |
| 8050094 | Memory cell array and non-volatile memory device A memory cell array, divided into multiple row memory cell arrays, includes multiple memory banks and sense amplifiers. Each of the memory banks includes multiple logical sectors and at least two sub-memory banks of multiple sub-memory banks. The at least two sub-me... | 11/01/2011 |
| 8045382 | Flash memory devices and erasing methods thereof Disclosed is an erasing method for a flash memory device that includes erasing memory cells of a selected memory block and post-programming the erased memory cells to have a threshold voltage distribution with the lowest level that is at or near 0V. The post-program... | 10/25/2011 |
| 8040743 | Data storage using read-mask-write operation Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second... | 10/18/2011 |
| 8036035 | Erase cycle counter usage in a memory device Memory devices and methods are disclosed to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for eac... | 10/11/2011 |
| 8036037 | Method of programming flash memory device A method of programming data in a flash memory device is disclosed. The memory device includes a memory cell array which in turn includes at least one block, and the block in turn includes a plurality of pages. A program command to program a plurality of pages in th... | 10/11/2011 |
| 8036038 | Semiconductor memory device A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selecto... | 10/11/2011 |
| 8036036 | Semiconductor device and a manufacturing method thereof A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in serie... | 10/11/2011 |
| 8031525 | Flash memory device and program method thereof A flash memory device that includes a voltage generator circuit configured to generate a program voltage, a pass voltage, and a high voltage; a plurality of planes configured to perform a program operation in response to the program, pass, and high voltages and to v... | 10/04/2011 |
| 8027199 | Semiconductor memory device An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a... | 09/27/2011 |
| 8018769 | Non-volatile memory with linear estimation of initial programming voltage In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time... | 09/13/2011 |
| 8014201 | Nonvolatile memory device extracting parameters and nonvolatile memory system including the same The nonvolatile memory device includes a memory cell array having a plurality of memory blocks and a control logic circuit configured to store a parameter to access at least one of the plurality of memory blocks, configured to detect a variation of the parameter whi... | 09/06/2011 |
| 8014202 | Non-volatile semiconductor memory device In a non-volatile semiconductor memory device, variations in voltage applied to a bit line when an erase voltage applying step is repeatedly executed are suppressed, thereby reducing variations in Vt after erasure. A memory array includes memory cells arranged in an... | 09/06/2011 |
| 8009475 | Device selection circuit and method Embodiments of the invention take advantage of an unused state of an interface protocol (or specification), such as the ONFI specification, to control a selector circuit to assert one of a plurality of relatively localized device selection signals (e.g., chip enable... | 08/30/2011 |
| 8004894 | Semiconductor integrated circuit In the semiconductor integrated circuit incorporating non-volatile memory that is not electrically rewritable, updating stored data and reusing the non-volatile memory are made possible. The data stored in the non-volatile memory can be updated and the non-volatile ... | 08/23/2011 |
| 8004895 | Flash memory data correction and scrub techniques In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid da... | 08/23/2011 |
| 8004897 | Interleaved memory program and verify method, device and system An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the fir... | 08/23/2011 |
| 8004896 | Method of controlling operation of flash memory device According to a method of controlling the operation of a flash memory device including a number of memory blocks, a memory block of the memory blocks is first selected as a reference block. A program operation is performed on a memory cell included in the reference b... | 08/23/2011 |
