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| Number | Title | Issue Date |
| 8159877 | Method of directly reading output voltage to determine data stored in a non-volatile memory cell An NVM cell design enables direct reading of cell output voltage to determine data stored in the cell, while providing low current consumption and a simple program sequence that utilizes reverse Fowler-Nordheim tunneling. ... | 04/17/2012 |
| 8107290 | Memory cell structure, a memory device employing such a memory cell structure, and an integrated circuit having such a memory device A memory cell structure for a memory device includes a read transistor having a floating gate node, a tunnelling capacitor, and a coupling capacitor stack. The tunnelling capacitor is connected to the floating gate node and has a first programming terminal, and the ... | 01/31/2012 |
| 7889553 | Single-poly non-volatile memory cell A non-volatile memory cell includes: a substrate including diffusion regions for a read-out transistor; a capacitor formed in a poly-silicon layer adjacent the substrate, the capacitor including a floating gate for the read-out transistor and a control gate, the flo... | 02/15/2011 |
| 7813177 | Analog single-poly EEPROM incorporating two tunneling regions for programming the memory device A single-poly EEPROM memory device comprises a control gate isolated within a well of a first conductivity type in a semiconductor body of a second conductivity type, first and second tunneling regions isolated from one another within respective wells of the first c... | 10/12/2010 |
| 7652921 | Multi-level non-volatile memory cell with high-VT enhanced BTBT device The present disclosure provides a Non-Volatile Memory (NVM) cell and programming method thereof. The cell can denote at least two logic levels. The cell has a read-transistor with a floating gate, and Band-To-Band-Tunneling device (BTBT device) sharing the floating ... | 01/26/2010 |
| 7639536 | Storage unit of single-conductor non-volatile memory cell and method of erasing the same A storage unit of a single-conductor non-volatile memory cell is described, which includes an isolation layer in a substrate, a storage transistor and an erasing transistor. The storage transistor includes a first well of a first conductivity type in the substrate b... | 12/29/2009 |
| 7623380 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is us... | 11/24/2009 |
| 7542342 | Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of th... | 06/02/2009 |
| 7483299 | Devices and operation methods for reducing second bit effect in memory device A method for operating a semiconductor memory device having first and second bit lines, a gate electrode, an insulative layer, and a substrate includes applying first, second, and third biases to the first bit line, the second bit line, and the gate electrode, respe... | 01/27/2009 |
| 7436710 | EEPROM memory device with cell having NMOS in a P pocket as a control gate, PMOS program/erase transistor, and PMOS access transistor in a common well A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a commo... | 10/14/2008 |
| 7388784 | Nonvolatile semiconductor memory device including memory cell units each having a given number of memory cell transistors A nonvolatile semiconductor memory device includes a plurality of memory cell units and a memory cell array in which the memory cell units are arranged in matrix. Each of the memory cell units has a given number of electrically writable and erasable memory cell tran... | 06/17/2008 |
| 7368789 | Non-volatile programmable memory cell and array for programmable logic array A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be ... | 05/06/2008 |
| 7366025 | Reduced power programming of non-volatile cells Methods for minimizing current consumption in a memory array during programming of non-volatile memory cells, such as NROM cells, in the array include: programming a cell without having a direct current flowing from a positive supply to ground through the array, pro... | 04/29/2008 |
| 7365383 | Method of forming an EPROM cell and structure therefor An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate. ... | 04/29/2008 |
| 7366015 | Semiconductor integrated circuit device, production and operation method thereof A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells fun... | 04/29/2008 |
| 7358823 | Programmable capacitors and methods of using the same In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the tra... | 04/15/2008 |
| 7348621 | Non-volatile memory cells A non-volatile memory cell and method of fabrication are provided. The non-volatile memory cell includes a substrate of a first conductivity type, a first dopant region of a second conductivity type in the substrate, a second dopant region of the first conductivity ... | 03/25/2008 |
| 7339825 | Nonvolatile semiconductor memory with write global bit lines and read global bit lines A nonvolatile semiconductor memory is capable of dual and triple operation with a small chip size. A plurality of sectors is formed. Each sector has nonvolatile memory cells, local bit lines connected to these memory cells, and switch circuits. Write global bit line... | 03/04/2008 |
| 7339829 | Ultra low power non-volatile memory module An improved ultra-low power NVM module, which exhibits low power consumption and reduced layout area. An array of compact flash memory cells are programmed and erased in response to positive and negative boosted voltages. However, the compact flash memory cells are ... | 03/04/2008 |
| 7324397 | Semiconductor integrated circuit A semiconductor integrated circuit has a nonvolatile memory and a logic circuit which uses information stored in the nonvolatile memory to perform logical operation. The nonvolatile memory comprises bit lines, word lines, and memory cells. The memory cell comprises ... | 01/29/2008 |
| 7321510 | Read operation for non-volatile storage that includes compensation for coupling Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing ele... | 01/22/2008 |
| 7315267 | Mixed-mode semiconductor memory A mixed-mode semiconductor memory includes a memory bank array, an analog/digital converter, a digital/analog converter, a plurality of digital buses and a control unit. The memory bank array includes a plurality of memory banks that are each composed of a plurality... | 01/01/2008 |
| 7305502 | Compressing an amount of uncompressed data less than amount of hibernation related data written to storage via DMA controller when requested write is pending An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed, while freeing the system processor to perform other tasks, including c... | 12/04/2007 |
| 7301194 | Shrinkable and highly coupled double poly EEPROM with inverter A nonvolatile EEPROM cell having a double poly arrangement provides stored data without sense amplifiers, thereby reducing power requirements. The EEPROM cell has a floating gate in a first poly layer, and a control gate overlapping the floating gate in a second pol... | 11/27/2007 |
| 7301811 | Cost efficient nonvolatile SRAM cell A cost efficient nonvolatile memory cell may include an inverter, an access gate coupled to the inverter for controlling access to the memory cell, and a control gate. The inverter may include a floating gate at an input of the inverter, the floating gate formed in ... | 11/27/2007 |
| 7301821 | Volatile data storage in a non-volatile memory cell array A method for storing data on nodes in memory cells of a non-volatile memory cell array including steps of setting non-volatile devices of the non-volatile memory cell array to a desired state, biasing pull-up devices and non-volatile devices in a first set of rows o... | 11/27/2007 |
| 7292475 | Nonvolatile memory device and data write method for nonvolatile memory device A nonvolatile memory device, including a plurality of memory cell blocks, N memory cell blocks (N is an integer equal to or greater than 2) being arranged in a row direction, L memory cell blocks (L is an integer equal to or greater than 2) being arranged in a colum... | 11/06/2007 |
| 7285818 | Non-volatile two-transistor programmable logic cell and array layout A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transisto... | 10/23/2007 |
| 7285816 | Content addressable matrix memory cell A CAM memory cell integrated on a semiconductor substrate includes a plurality of floating gate memory cells, matrix-organized in rows, called word lines, and columns, called bit lines. The cells belonging to a same row and have floating gate electrodes are short-ci... | 10/23/2007 |
| 7282401 | Method and apparatus for a self-aligned recessed access device (RAD) transistor gate A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and... | 10/16/2007 |
| 7280421 | Non-volatile memory cell integrated with a latch A configuration circuit includes a latch and a dedicated non-volatile memory cell. The non-volatile memory cell is initially programmed or erased. The latch is then set to store a first logic value by coupling the latch to a first voltage supply terminal in response... | 10/09/2007 |
| 7269063 | Floating gate memory with split-gate read transistor and split gate program transistor memory cells and method for making the same Variations in memory array and cell configuration are shown, which eliminate punch-through disturb, reverse-tunnel. Several configurations are shown which range from combined and separate source lines for each row of cells, a two transistor cell containing a read tr... | 09/11/2007 |
| 7262457 | Non-volatile memory cell A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is form... | 08/28/2007 |
| 7262993 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device including: a first capacitor, one end of the first capacitor being connected to a floating node; a detection transistor, a gate electrode of the detection transistor being connected to the floating node; a second capacitor, ... | 08/28/2007 |
| 7257033 | Inverter non-volatile memory cell and array system NVM arrays include rows and columns of NVM cells comprising a floating gate, dual transistor, inverter storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for ... | 08/14/2007 |
| 7256415 | Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a m... | 08/14/2007 |
| 7242629 | High speed latch circuits using gated diodes A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal... | 07/10/2007 |
| 7233521 | Apparatus and method for storing analog information in EEPROM memory A storage device that is capable of receiving an analog signal and storing it as a digital signal. The storage device includes an input node configured to receive an analog input voltage and two non-volatile storage cells. A second non-volatile memory cell is couple... | 06/19/2007 |
| 7233528 | Reduction of programming time in electrically programmable devices A flash memory programming process incorporates two charge pumps per byte of bit cells. Placing a data “one” value in each bit cell erases an entire memory device. Before programming each cell, a prospective data content is scrutinized. If a data “zero” is t... | 06/19/2007 |
| 7233527 | Nonvolatile memory structure The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word... | 06/19/2007 |
