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| Number | Title | Issue Date |
| 8081510 | Semiconductor integrated circuit and unstable bit detection method for the same A semiconductor integrated circuit including a nonvolatile memory cell is provided with a detection/word line voltage control circuit for sequentially supplying two or more mutually different unstable bit detecting voltages to a control gate of the nonvolatile memor... | 12/20/2011 |
| 8018768 | Non-volatile static random access memory (NVSRAM) device A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit can provide fast data access. When the power supply is somehow interru... | 09/13/2011 |
| 7916539 | Differential, level-shifted EEPROM structures Memory embodiments are provided to operate in memory systems which are configured to have a system ground and a system substrate that are biased at different voltages. At least one of these embodiments includes a memory cell and write and read circuits in which the ... | 03/29/2011 |
| 7778076 | Memory unit A memory unit is provided herein. Two non-volatile devices are used to store a logic state of the memory unit into the non-volatile devices. Although a power supply for the memory unit is shut down, the non-volatile devices still keep the data stored therein. The pr... | 08/17/2010 |
| 7692964 | Source-biased SRAM cell with reduced memory cell leakage A Static Random Access Memory (SRAM) cell having a source-biasing mechanism for leakage reduction. In standby mode, the cell's wordline is deselected and a source-biasing potential is provided to the cell. In read mode, the wordline is selected and responsive theret... | 04/06/2010 |
| 7602640 | Non-volatile storage element A non-volatile storage element includes a first data terminal and a second data terminal, a first MOS transistor and a second MOS transistor, the first MOS transistor and the second MOS transistor having a first conductivity type, a third MOS transistor and a four M... | 10/13/2009 |
| 7539054 | Method and apparatus to program and erase a non-volatile static random access memory from the bit lines A system and method for programming and erasing a semiconductor memory is disclosed. More particularly, the present invention uses the bit lines of a volatile memory portion of semiconductor memory so as to program and erase the non-volatile portion of the semicondu... | 05/26/2009 |
| 7518916 | Method and apparatus to program both sides of a non-volatile static random access memory A system and method for programming both sides of the non-volatile portion in a semiconductor memory is disclosed. The present invention erases and then programs the memory stacks in the non-volatile portion of an nvSRAM. ... | 04/14/2009 |
| 7417890 | Semiconductor memory device A semiconductor memory device is disclosed, which includes a first SRAM cell which includes cross-connected first and second inverters having first and second nodes, a first transistor connected between a first bit line and the first node and having a gate connected... | 08/26/2008 |
| 7394708 | Adjustable global tap voltage to improve memory cell yield A system that increases device yield by correcting improper operation of the device's memory cells due to process variations is disclosed. The device includes an array of memory cells and an adjustable bias voltage circuit, and is coupled to a test circuit that gene... | 07/01/2008 |
| 7379336 | Integrated DRAM-NVRAM multi-level memory An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a... | 05/27/2008 |
| 7370016 | Music distribution systems Music is blanket transmitted (for example, via satellite downlink transmission) to each customer's user station where selected music files are recorded. Customers preselect from a list of available music in advance using an interactive screen selector, and pay only ... | 05/06/2008 |
| 7365585 | Apparatus and method for charge pump slew rate control An apparatus and method for improving memory cell reliability is disclosed. The slew rate is reduced in an applied voltage signal used to program a memory cell when Fowler-Nordheim (FN) tunneling injection is detected. The applied programming signal is provided by a... | 04/29/2008 |
| 7362154 | Radiation hardened latch A programmable phase frequency divider for space applications is implemented in CMOS technology, and consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division r... | 04/22/2008 |
| 7342821 | Hot-carrier-based nonvolatile memory utilizing differing transistor structures A memory circuit includes a latch having a first node and a second node, a first MIS transistor operable to couple between the first node and a predetermined node, a second MIS transistor operable to couple between the second node and the predetermined node, and a c... | 03/11/2008 |
| 7339820 | Nonvolatile memory and semiconductor device A nonvolatile memory capable of acting at each 1 bit and having a high integration density. A small-sized semiconductor device of multiple high functions having such nonvolatile memory. The nonvolatile memory is constructed to have a memory cell composed of t... | 03/04/2008 |
| 7336533 | Electronic device and method for operating a memory circuit An electronic device includes a memory cell that utilizes a bi-directional low impedance, low voltage drop full pass gate to connect a bit cell to a bit write line during a write phase, and during a read phase the full pass gate can remain off and a high input imped... | 02/26/2008 |
| 7336542 | Nonvolatile latch A nonvolatile latch includes a memory element for storing an input data value. A write protect element is coupled to the memory element for utilizing a write protect signal to ensure the input data value stored by the memory element remains during a loss of a supply... | 02/26/2008 |
| 7336525 | Nonvolatile memory for logic circuits A memory circuit that retains stored data upon power down includes a volatile data storage circuit; and at least one nonvolatile memory coupled within the volatile data storage circuit, wherein the at least one nonvolatile memory includes a high resistive state and ... | 02/26/2008 |
| 7336534 | Non-volatile memory device and drive method thereof A non-volatile memory device and drive method thereof uses a voltage bias condition to enable an electronic device to normally operate without employing a specific transistor, e.g., a recall transistor. The non-volatile memory device performs its function normally w... | 02/26/2008 |
| 7336539 | Method of operating flash memory cell A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked g... | 02/26/2008 |
| 7321504 | Static random access memory cell A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter h... | 01/22/2008 |
| 7321505 | Nonvolatile memory utilizing asymmetric characteristics of hot-carrier effect A memory circuit includes a latch having a first node and a second node, a first MIS transistor having source/drain nodes thereof coupled to the first node and to a plate line, respectively, and a gate node thereof coupled to a word selecting line, a second MIS tran... | 01/22/2008 |
| 7313021 | Nonvolatile memory circuit A nonvolatile memory circuit includes a flip-flop to degrade an internal circuit irreversibly based on a voltage applied to a first or second bit line so as to latch data in a nonvolatile manner, a first switch coupled between a first output terminal of the flip-flo... | 12/25/2007 |
| 7307451 | Field programmable gate array device The present invention proposes a Field Programmable Gate Array device comprising a plurality of configurable electrical connections, a plurality of controlled switches, each one adapted to activating/de-activating at least one respective electrical connection in res... | 12/11/2007 |
| 7301797 | Method of operating semiconductor integrated circuit including SRAM block and semiconductor integrated circuit including SRAM block A method of operating a semiconductor integrated circuit including a SRAM block, in which non-volatile data is stored in the SRAM block, is disclosed. In an exemplary embodiment, the non-volatile data is stored by flowing a drain current in one of a pair of pull-dow... | 11/27/2007 |
| 7291882 | Programmable and erasable digital switch device and fabrication method and operating method thereof A programmable and erasable digital switch device is provided. An N-type memory transistor and a P-type memory transistor are formed over a substrate. The N-type memory transistor includes a first N-type doped region, a second N-type doped region, a first charge sto... | 11/06/2007 |
| 7286390 | Memory cell and semiconductor integrated circuit device A memory cell includes a memory cell section and a switching section. The memory cell section includes first and second inverters which are connected to form a flip-flop, and each of the first and second inverters comprises a load transistor and a drive transistor. ... | 10/23/2007 |
| 7269040 | Static content addressable memory cell A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second access transistors, each coupled between a data node of the latch and a respective data line. The gates of ... | 09/11/2007 |
| 7245520 | Random access memory including nanotube switching elements A random access memory cell includes first and second nanotube switching elements and an electronic memory with cross-coupled first and second inverters. Each nanotube switching element includes a nanotube channel element having at least one electrically conductive ... | 07/17/2007 |
| 7242614 | Rewriteable electronic fuses Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predet... | 07/10/2007 |
| 7236396 | Area efficient implementation of small blocks in an SRAM array An SRAM array with a dummy cell row structure in which the SRAM array is divided into segments isolated by a row pattern of dummy cells. The dummy cell structure provides a continuous cell array at the lower cell patterning levels. The SRAM array includes a first an... | 06/26/2007 |
| 7221586 | Memory utilizing oxide nanolaminates Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region b... | 05/22/2007 |
| 7222271 | Method for repairing hardware faults in memory chips Method for repairing hardware faults in memory chips. According to one embodiment, a method is provided for repairing bit errors in memory chips having a multiplicity of memory cells. The method can include detecting bit errors using an error identification algorith... | 05/22/2007 |
| 7216284 | Content addressable memory having reduced power consumption A content addressable memory (CAM). A data portion of the CAM array includes word data storage. Each word line includes CAM cells (dynamic or static) in the data portion and a common word match line. An error correction (e.g., parity) portion of the CAM array contai... | 05/08/2007 |
| 7215594 | Address latch circuit of memory device An address latch circuit of a memory device is disclosed. A latch operation is disabled while an address signal makes a level transition in the memory device, and then enabled when the address signal is stabilized after the level transition. Therefore, it is possibl... | 05/08/2007 |
| 7209403 | Enhanced fuse configurations for low-voltage flash memories An enhanced fuse circuit is discussed that advances redundancy techniques in integrated circuits. The enhanced fuse circuit uses a single nonvolatile fuse and a latch that is coupled at a desired time. One embodiment of the invention discusses a fuse circuit that in... | 04/24/2007 |
| 7209387 | Non-volatile programmable fuse apparatus in a flash memory with pairs of supercells programmed in a complementary fashion The non-volatile, programmable fuse apparatus has a pair of p-channel transistors coupled in a latch configuration. A supercell is coupled between each transistor and ground. Each supercell is comprised of a plurality of non-volatile memory cells that are each progr... | 04/24/2007 |
| 7209900 | Music distribution systems Music is blanket transmitted (for example, via satellite downlink transmission) to each customer's user station where selected music files are recorded. Customers preselect from a list of available music in advance using an interactive screen selector, and pay only ... | 04/24/2007 |
| 7206217 | Non-volatile flip flop A non-volatile flip flop according to the invention comprising: a flip flop section (4) having a pair of memory nodes (5, 6) for storing a pair of inverse logic data elements; and a pair of non-volatile resistance change elements (11, 12) which ... | 04/17/2007 |
