Celebrity Inventors
Glam girl Heddy Lamar may have used her good looks to good effect on the silver screen, but she put her smarts to better use as an inventor. During World War II, she co-patented a frequency-switching system for torpedo guidance that was considered years ahead of its time.
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| Number | Title | Issue Date |
| 8189409 | Readout circuit for rewritable memories and readout method for same In one embodiment, a readout circuit for rewritable memories comprises a control logic unit with an input for supplying a start signal and with several outputs for providing a respective control signal as a function of start signal, a first terminal for switchable c... | 05/29/2012 |
| 8189385 | Nonvolatile semiconductor memory device, method for manufacturing the same, and nonvolatile memory array A floating gate made of polysilicon is provided on a semiconductor substrate through the medium of a gate insulator. A side-wall insulating film is provided on each side wall of the floating gate. A first impurity diffusion layer, which occupies a space within the s... | 05/29/2012 |
| 8174884 | Low power, single poly EEPROM cell with voltage divider An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIGS. 7 and 8) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (806) coupled to receive... | 05/08/2012 |
| 8174885 | High speed operation method for twin MONOS metal bit array The present invention provides a novel read method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the... | 05/08/2012 |
| 8169823 | Memory devices having volatile and non-volatile memory characteristics and methods of operating the same Multi-bit semiconductor memory devices having both volatile and nonvolatile memory characteristics and methods of operating the same are disclosed, the semiconductor memory device including a floating body on an upper region of a substrate, a gate electrode on the f... | 05/01/2012 |
| 8169824 | Semiconductor device including contact plug having an elliptical sectional shape A semiconductor device includes a first MOS transistor, second MOS transistors, first contact plugs, and a second contact plug. The first MOS transistor with a first conductivity is formed on a semiconductor substrate. The second MOS transistors with a second conduc... | 05/01/2012 |
| 8154924 | Nonvolatile memory device and read method Disclosed is a nonvolatile memory including a memory cell array including a first cell string connected between a first bit line and a first common source line, and a second cell string a second common source line and a second bit line adjacent to the first bit line... | 04/10/2012 |
| 8144493 | CAM cell memory device A code address memory (CAM) cell memory device comprises a first storage unit comprising a first nonvolatile memory cell configured to output a power source voltage in response to a read voltage, and a second storage unit comprising a second nonvolatile memory cell ... | 03/27/2012 |
| 8139411 | pFET nonvolatile memory A non-volatile memory integrated circuit includes multiple memory cells, each memory cell including a first MOS transistor, a first control capacitor, and a first floating gate coupled to the first MOS transistor and the first control capacitor. A first read/write c... | 03/20/2012 |
| 8139410 | Trap-charge non-volatile switch connector for programmable logic A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconducto... | 03/20/2012 |
| 8139409 | Access signal adjustment circuits and methods for memory cells in a cross-point array Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory ... | 03/20/2012 |
| 8139408 | Scalable electrically eraseable and programmable memory A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a secon... | 03/20/2012 |
| 8134870 | High-density non-volatile read-only memory arrays and related methods In an embodiment, a read-only memory array includes a plurality of word lines, a plurality of bit-lines including first and second bit-lines, and a plurality of memory cells configured to represent data values. Each memory cell can include a transistor having a cont... | 03/13/2012 |
| 8130547 | Method of maintaining the state of semiconductor memory having electrically floating body transistor Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates... | 03/06/2012 |
| 8130546 | Semiconductor memory device and manufacturing method of semiconductor memory device A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers ... | 03/06/2012 |
| 8120956 | Single-transistor EEPROM array and operation methods An integrated circuit structure includes an electrically erasable programmable read-only memory (EEPROM) array, which includes EEPROM cells arranged as rows and columns; a plurality of word-lines and a plurality of drain-lines extending in a column direction, and a ... | 02/21/2012 |
| 8120955 | Array and control method for flash based FPGA cell A push-pull non-volatile memory array includes memory cells with an n-channel non-volatile pull-down transistor in series with a p-channel volatile pull-up transistor. A non-volatile transistor row line is associated with each row of the array and is coupled to the ... | 02/21/2012 |
| 8111552 | Offset non-volatile storage A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufact... | 02/07/2012 |
| 8107288 | Static memory devices A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One o... | 01/31/2012 |
| 8107289 | Nonvolatile memory device A nonvolatile memory device having a three-dimensional structure includes first word line stacks in which first word lines are stacked; second word line stacks in which second word lines parallel to the first word lines are stacked; first connection lines connecting... | 01/31/2012 |
| 8102709 | Transistor having peripheral channel Transistors for use in semiconductor integrated circuit devices including a first source/drain region of the transistor is formed around a perimeter of a channel region, and a second source/drain region formed to extend below the channel region such that the channel... | 01/24/2012 |
| 8094497 | Multi-gate bandgap engineered memory Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure... | 01/10/2012 |
| 8094498 | Nonvolatile semiconductor memory device In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second... | 01/10/2012 |
| 8094496 | Nonvolatile semiconductor memory device and control method thereof A nonvolatile semiconductor memory device includes a multi-layer insulating film having at least charge storage layers and formed on bottom surfaces and both side surfaces of a plurality of trench portions respectively formed in portions between the plurality of act... | 01/10/2012 |
| 8089809 | Trap-charge non-volatile switch connector for programmable logic A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconducto... | 01/03/2012 |
| 8089808 | Nonvolatile semiconductor memory device, and reading method, writing method and erasing method of nonvolatile semiconductor memory device A nonvolatile semiconductor memory including a memory cell array of memory cells arranged in a matrix, each of which includes a selective transistor and a memory cell transistor; the first column decoder for controlling the potentials of the bit lines and the source... | 01/03/2012 |
| 8081509 | Non-volatile memory device and method of operation therefor In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside t... | 12/20/2011 |
| 8072806 | Semiconductor memory device and method for driving semiconductor memory device A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source line... | 12/06/2011 |
| 8072807 | FLOTOX type EEPROM A FLOTOX EEPROM of the invention includes: a plurality of floating gates 11 arranged in array, each having a tunnel window 12 and allowing electron injection and extraction via the tunnel window; a plurality of select gates 13 provided in one-on... | 12/06/2011 |
| 8064254 | Columnar non-volatile memory devices with auxiliary transistors and methods of operating the same A non-volatile memory device includes at least one semiconductor column having a first sidewall and a second sidewall. The device also includes at least one gate electrode is disposed on the first sidewall and at least one control gate electrode disposed on the seco... | 11/22/2011 |
| 8054687 | Systems and methods of providing programmable voltage and current reference devices The present invention describes systems and methods to for providing stable and programmable voltage and current reference devices. An exemplary embodiment of the present invention provides a voltage reference device having a first floating-gate transistor with a fi... | 11/08/2011 |
| 8050091 | EEPROM devices and methods of operating and fabricating the same An electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active region... | 11/01/2011 |
| 8045379 | Semiconductor device that is advantageous in operational environment at high temperatures A semiconductor device includes an N-type insulated-gate field-effect transistor including a first insulating layer that is provided along side walls of a gate electrode, has a negative thermal expansion coefficient, and applies a tensile stress to a channel region ... | 10/25/2011 |
| 8045380 | Flash memory device and program method of flash memory device using different voltages A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least... | 10/25/2011 |
| 8040726 | Flash memory device and layout method of the flash memory device Provided is a flash memory device including a plurality of page buffer high voltage transistors. The plurality of high voltage transistors are operatively associated with a page buffer circuit, wherein each high voltage transistor includes; a gate pattern separating... | 10/18/2011 |
| 8036031 | Semiconductor device having a field effect source/drain region A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain reg... | 10/11/2011 |
| 8027197 | Nonvolatile memory device A nonvolatile memory device having a three-dimensional structure includes first word line stacks in which first word lines are stacked; second word line stacks in which second word lines parallel to the first word lines are stacked; first connection lines connecting... | 09/27/2011 |
| 8027198 | Trap-charge non-volatile switch connector for programmable logic A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconducto... | 09/27/2011 |
| 8023326 | Trap-charge non-volatile switch connector for programmable logic A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconducto... | 09/20/2011 |
| 8018767 | Semiconductor device and method of controlling the same The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or fr... | 09/13/2011 |
